JMR-dev/ReLibreHardwareMonitor
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27 Commits
Author SHA1 Message Date
namazsoandPhyxionNL eb5e1a20be Swap WinRing0 to PawnIO (#1857) 
* Replace WinRing0 with PawnIO

* Update RAMSPDToolkit

* Add install check + cleanup

* Move folder + formatting

* Add back missing TryLoadDll

* Update PawnIo.cs

* Add third party notices file

* Remove the how to apply section

* Drop silent

* Don't crash if PawnIO isn't installed

* Formatting

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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2025-09-16 11:58:31 +02:00
Niu Haoyu 2d4f2cfb21 Intel Ultra 9 200 Series ArrowLake Added (#1630) 2025-02-07 16:00:20 +01:00
Markus H. 8d612d20da added support for Intel ElkhartLake (#1625) 
* Intel Arrow Lake 200 added

* added SAPPHIRERAPIDS support

* changed naming from SAPPHIRERAPIDS to SapphireRapids

* added support for ElkhartLake
 2025-02-04 16:30:00 +01:00
Markus H. 08c1ee2805 SAPPHIRERAPIDS support added (#1555) 
* Intel Arrow Lake 200 added

* added SAPPHIRERAPIDS support

* changed naming from SAPPHIRERAPIDS to SapphireRapids
 2025-01-16 15:10:53 +01:00
blakekrpecandPhyxionNL 06ed4744b1 Individual Sensor Requests (#1504) 
* added /Sensor endpoints

* fix intel sensor order

* Update HttpServer.cs

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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2024-11-24 11:04:46 +01:00
Howon Lee cc303f75c5 Added support for Lunar Lake CPUs (#1520) 
* Added support for Lunar Lake CPUs

* Fixed a typo
 2024-11-12 18:45:16 +01:00
Markus H. 0c32773dc2 Intel Arrow Lake 200 added (#1495) 2024-10-17 12:44:53 +02:00
SeongChan LeeandPhyxionNL 65058eb1f7 Add MSR_PLATFORM_ENERGY_COUNTER 0x64D (#1357) 
* Add MSR_PLATFORM_ENERGY_COUNTER (0x64D)

MSR_PLATFORM_ENERGY_COUNTER 0x64D is a platform energy counter register according to
p. 2-272, "Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4: Model-Specific Registers"
It's description is:
> Total energy consumed by all devices in the platform
> that receive power from integrated power delivery
> mechanism, included platform devices are processor
> cores, SOC, memory, add-on or peripheral devices that
> get powered directly from the platform power delivery
> means. The energy units are specified in the
> MSR_RAPL_POWER_UNIT.Enery_Status_Unit.

* Update IntelCpu.cs

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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2024-06-11 16:30:53 +02:00
sebastian-devandPhyxionNL dd5b3e1610 Intel Gen 14 Meteor Lake (#1253) 
* Intel Gen 14 Meteor Lake
New Intel Gen.14 CPU Model ID

* Update IntelCpu.cs

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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2024-01-29 11:48:35 +01:00
PhyxionNL cd77cec0b5 Unify CPU namespace with folder (#1023) 2023-03-21 18:11:40 +01:00
PhyxionNL 58cef111a1 Use file-scoped namespaces (#842) 2022-10-09 13:22:57 +02:00
PhyxionNL 3ac329f247 Fix some code analysis issues (#841) 2022-10-09 13:16:31 +02:00
PhyxionNL a6f28dc7e6 Add RaptorLake and one more Alder Lake (#815) 2022-09-14 12:14:46 +02:00
DevTechProfile e9e8e034ef Added Alder Lake-H model ID (#779) 2022-07-15 10:09:26 +02:00
PhyxionNL 38b97e10d0 Update editorconfig + changes (#771) 2022-06-29 19:38:57 +02:00
EMN-CSharp eed7742e7e Add support for VID sensors per core on Intel CPUs (#741) 
* Add support for VID sensors per core on Intel CPUs

* Remove pointless variable assignment
 2022-05-12 09:57:08 +02:00
Bjarni Ivarsson e68fd4e8ef "CPU Core" voltage sensor for intel CPU's (#682) 
* first attempt

* review updates
 2022-03-01 09:59:41 +01:00
Bjarni Ivarsson 627f0a56ce Add Intel integrated GPU (#671) 
Thanks to @bjarniivarsson.
 2022-02-26 10:14:09 +01:00
PhyxionNL 23f515612c Add Alder Lake and Jasper Lake (#589) 
Fixes #588
 2021-11-03 10:49:50 +01:00
sebastian-dev ab6a89ea3f Intel Gen11 Rocket Lake Support (#421) 
Thanks to @sebastian-dev
 2021-04-09 10:45:40 +02:00
Phyxion fe662558f4 Added experimental support for Intel 06_A5h CPUs 
Thanks to @moellerm.
 2020-05-25 11:28:45 +02:00
Phyxion 3cc3d9139c Add support for multiple processor groups. 
Merge from upstream.
 2020-05-11 13:29:52 +02:00
Phyxion 42e6a3eb19 Add support for Intel Comet Lake 
Also add CORS header for https://github.com/openhardwaremonitor/openhardwaremonitor/issues/1234
 2020-03-02 17:14:00 +01:00
Phyxion 5bd108167d Restore OHM in copyright statement 2020-02-28 11:39:25 +01:00
Stefan Hirschmann 404b2a766b Add support for Intel Goldmont, Goldmont Plus, Cannon Lake, Ice Lake, Tiger Lake and Tremont microarchitectures (#170) 
Thanks to @hirschmann
 2019-11-21 14:34:46 +01:00
Phyxion 059b43cc14 Unify remaining memory names 2019-10-11 12:39:56 +02:00
Phyxion 73378f7c7b Code style #130 (#132) 
This closes #99.
 2019-09-23 19:29:10 +02:00