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Add RaptorLake and one more Alder Lake (#815)

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This commit is contained in:
PhyxionNL
2022-09-14 12:14:46 +02:00
committed by GitHub
parent ae3bc27719
commit a6f28dc7e6
1 changed files with 14 additions and 2 deletions
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LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
+14 -2
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@@ -193,10 +193,18 @@ namespace LibreHardwareMonitor.Hardware.CPU
tjMax = GetTjMaxFromMsr();
break;
case 0x97: // Alder Lake-S (Intel 7/10nm)
case 0x9A: // Alder Lake-H (Intel 7/10nm)
case 0x97: // Alder Lake (7/10nm)
case 0x9A: // Alder Lake-L (7/10nm)
case 0xBE: // Alder Lake-N (7/10nm)
_microArchitecture = MicroArchitecture.AlderLake;
tjMax = GetTjMaxFromMsr();
break;
case 0xB7: // Raptor Lake (7nm)
case 0xBA: // Raptor Lake-P (7nm)
case 0xBF: // Raptor Lake-N (7nm)
_microArchitecture = MicroArchitecture.RaptorLake;
tjMax = GetTjMaxFromMsr();
break;
case 0x9C: // Jasper Lake (10nm)
@@ -266,6 +274,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
case MicroArchitecture.JasperLake:
case MicroArchitecture.KabyLake:
case MicroArchitecture.Nehalem:
case MicroArchitecture.RaptorLake:
case MicroArchitecture.RocketLake:
case MicroArchitecture.SandyBridge:
case MicroArchitecture.Silvermont:
@@ -377,6 +386,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
MicroArchitecture.IvyBridge or
MicroArchitecture.JasperLake or
MicroArchitecture.KabyLake or
MicroArchitecture.RaptorLake or
MicroArchitecture.RocketLake or
MicroArchitecture.SandyBridge or
MicroArchitecture.Silvermont or
@@ -577,6 +587,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
case MicroArchitecture.IvyBridge:
case MicroArchitecture.JasperLake:
case MicroArchitecture.KabyLake:
case MicroArchitecture.RaptorLake:
case MicroArchitecture.RocketLake:
case MicroArchitecture.SandyBridge:
case MicroArchitecture.Silvermont:
@@ -670,6 +681,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
Skylake,
TigerLake,
Tremont,
RaptorLake,
Unknown
}