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Add support for Intel Goldmont, Goldmont Plus, Cannon Lake, Ice Lake, Tiger Lake and Tremont microarchitectures (#170)

Browse Source 
Thanks to @hirschmann
This commit is contained in:
Stefan Hirschmann
2019-11-21 14:34:46 +01:00
committed by Phyxion
parent 14338554da
commit 404b2a766b
1 changed files with 63 additions and 33 deletions
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LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
+63 -33
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@@ -56,7 +56,6 @@ namespace LibreHardwareMonitor.Hardware.CPU
tjMax = Floats(85 + 10);
break;
}
break;
case 0x0B: // G0
tjMax = Floats(90 + 10);
@@ -68,7 +67,6 @@ namespace LibreHardwareMonitor.Hardware.CPU
tjMax = Floats(85 + 10);
break;
}
break;
case 0x17: // Intel Core 2 (45nm)
_microArchitecture = MicroArchitecture.Core;
@@ -88,7 +86,6 @@ namespace LibreHardwareMonitor.Hardware.CPU
tjMax = Floats(90);
break;
}
break;
case 0x1A: // Intel Core i7 LGA1366 (45nm)
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
@@ -143,21 +140,42 @@ namespace LibreHardwareMonitor.Hardware.CPU
_microArchitecture = MicroArchitecture.Skylake;
tjMax = GetTjMaxFromMsr();
break;
case 0x4C:
case 0x4C: // Intel Airmont (Cherry Trail, Braswell)
_microArchitecture = MicroArchitecture.Airmont;
tjMax = GetTjMaxFromMsr();
break;
case 0x8E:
case 0x9E: // Intel Core i5, i7 7xxxx (14nm)
case 0x8E: // Intel Core i5, i7 7xxxx (14nm) (Kaby Lake) and 8xxxx (14nm++) (Coffee Lake)
case 0x9E:
_microArchitecture = MicroArchitecture.KabyLake;
tjMax = GetTjMaxFromMsr();
break;
case 0x5C: // Intel ApolloLake
_microArchitecture = MicroArchitecture.ApolloLake;
case 0x5C: // Goldmont (Apollo Lake)
case 0x5F: // (Denverton)
_microArchitecture = MicroArchitecture.Goldmont;
tjMax = GetTjMaxFromMsr();
break;
case 0xAE: // Intel Core i5, i7 8xxxx (14nm++)
_microArchitecture = MicroArchitecture.CoffeeLake;
case 0x7A: // Goldmont plus (Gemini Lake)
_microArchitecture = MicroArchitecture.GoldmontPlus;
tjMax = GetTjMaxFromMsr();
break;
case 0x66: // Intel Core i3 8xxx (10nm) (Cannon Lake)
_microArchitecture = MicroArchitecture.CannonLake;
tjMax = GetTjMaxFromMsr();
break;
case 0x7D: // Intel Core i3, i5, i7 10xxx (10nm) (Ice Lake)
case 0x7E:
case 0x6A: // Ice Lake server
case 0x6C:
_microArchitecture = MicroArchitecture.IceLake;
tjMax = GetTjMaxFromMsr();
break;
case 0x86: // Tremont (10nm) (Elkhart Lake, Skyhawk Lake)
_microArchitecture = MicroArchitecture.Tremont;
tjMax = GetTjMaxFromMsr();
break;
case 0x8C: // Tiger Lake (10nm)
case 0x8D:
_microArchitecture = MicroArchitecture.TigerLake;
tjMax = GetTjMaxFromMsr();
break;
default:
@@ -166,8 +184,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
break;
}
}
break;
break;
case 0x0F:
{
switch (_model)
@@ -187,14 +204,12 @@ namespace LibreHardwareMonitor.Hardware.CPU
break;
}
}
break;
break;
default:
_microArchitecture = MicroArchitecture.Unknown;
tjMax = Floats(100);
break;
break;
}
// set timeStampCounterMultiplier
switch (_microArchitecture)
{
@@ -207,8 +222,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
_timeStampCounterMultiplier = ((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1);
}
}
break;
break;
case MicroArchitecture.Nehalem:
case MicroArchitecture.SandyBridge:
case MicroArchitecture.IvyBridge:
@@ -217,17 +231,20 @@ namespace LibreHardwareMonitor.Hardware.CPU
case MicroArchitecture.Silvermont:
case MicroArchitecture.Skylake:
case MicroArchitecture.Airmont:
case MicroArchitecture.ApolloLake:
case MicroArchitecture.Goldmont:
case MicroArchitecture.KabyLake:
case MicroArchitecture.CoffeeLake:
case MicroArchitecture.GoldmontPlus:
case MicroArchitecture.CannonLake:
case MicroArchitecture.IceLake:
case MicroArchitecture.TigerLake:
case MicroArchitecture.Tremont:
{
if (Ring0.ReadMsr(MSR_PLATFORM_INFO, out uint eax, out uint _))
{
_timeStampCounterMultiplier = (eax >> 8) & 0xff;
}
}
break;
break;
default:
_timeStampCounterMultiplier = 0;
break;
@@ -324,8 +341,13 @@ namespace LibreHardwareMonitor.Hardware.CPU
_microArchitecture == MicroArchitecture.Skylake ||
_microArchitecture == MicroArchitecture.Silvermont ||
_microArchitecture == MicroArchitecture.Airmont ||
_microArchitecture == MicroArchitecture.Goldmont ||
_microArchitecture == MicroArchitecture.KabyLake ||
_microArchitecture == MicroArchitecture.ApolloLake)
_microArchitecture == MicroArchitecture.GoldmontPlus ||
_microArchitecture == MicroArchitecture.CannonLake ||
_microArchitecture == MicroArchitecture.IceLake ||
_microArchitecture == MicroArchitecture.TigerLake ||
_microArchitecture == MicroArchitecture.Tremont)
{
_powerSensors = new Sensor[_energyStatusMsrs.Length];
_lastEnergyTime = new DateTime[_energyStatusMsrs.Length];
@@ -490,31 +512,35 @@ namespace LibreHardwareMonitor.Hardware.CPU
{
uint multiplier = eax & 0xff;
_coreClocks[i].Value = (float)(multiplier * newBusClock);
}
break;
}
case MicroArchitecture.SandyBridge:
case MicroArchitecture.IvyBridge:
case MicroArchitecture.Haswell:
case MicroArchitecture.Broadwell:
case MicroArchitecture.Silvermont:
case MicroArchitecture.Airmont:
case MicroArchitecture.Skylake:
case MicroArchitecture.ApolloLake:
case MicroArchitecture.Goldmont:
case MicroArchitecture.KabyLake:
case MicroArchitecture.CoffeeLake:
case MicroArchitecture.GoldmontPlus:
case MicroArchitecture.CannonLake:
case MicroArchitecture.IceLake:
case MicroArchitecture.TigerLake:
case MicroArchitecture.Tremont:
{
uint multiplier = (eax >> 8) & 0xff;
_coreClocks[i].Value = (float)(multiplier * newBusClock);
}
break;
}
default:
{
double multiplier = ((eax >> 8) & 0x1f) + 0.5 * ((eax >> 14) & 1);
_coreClocks[i].Value = (float)(multiplier * newBusClock);
}
break;
}
}
}
else
@@ -572,8 +598,12 @@ namespace LibreHardwareMonitor.Hardware.CPU
Skylake,
Airmont,
KabyLake,
ApolloLake,
CoffeeLake
Goldmont,
GoldmontPlus,
CannonLake,
IceLake,
TigerLake,
Tremont
}
// ReSharper disable InconsistentNaming