Intel Ultra 9 200 Series ArrowLake Added (#1630)

This commit is contained in:
Niu Haoyu
2025-02-07 16:00:20 +01:00
committed by GitHub
parent 24b5e04315
commit 2d4f2cfb21
@@ -222,6 +222,7 @@ internal sealed class IntelCpu : GenericCpu
tjMax = GetTjMaxFromMsr();
break;
case 0xC5: // Intel Core Ultra 9 200 Series ArrowLake
case 0xC6: // Intel Core Ultra 7 200 Series ArrowLake
_microArchitecture = MicroArchitecture.ArrowLake;
tjMax = GetTjMaxFromMsr();
@@ -234,7 +235,7 @@ internal sealed class IntelCpu : GenericCpu
case 0x8F: // Intel Xeon W5-3435X // SapphireRapids
_microArchitecture = MicroArchitecture.SapphireRapids;
tjMax = GetTjMaxFromMsr();
break;
break;
case 0x96: // Intel Celeron ElkhartLake
_microArchitecture = MicroArchitecture.ElkhartLake;
tjMax = GetTjMaxFromMsr();
@@ -306,7 +307,7 @@ internal sealed class IntelCpu : GenericCpu
case MicroArchitecture.Silvermont:
case MicroArchitecture.Skylake:
case MicroArchitecture.TigerLake:
case MicroArchitecture.SapphireRapids:
case MicroArchitecture.SapphireRapids:
case MicroArchitecture.ElkhartLake:
case MicroArchitecture.Tremont:
if (Ring0.ReadMsr(MSR_PLATFORM_INFO, out eax, out uint _))
@@ -424,7 +425,7 @@ internal sealed class IntelCpu : GenericCpu
MicroArchitecture.Silvermont or
MicroArchitecture.Skylake or
MicroArchitecture.TigerLake or
MicroArchitecture.SapphireRapids or
MicroArchitecture.SapphireRapids or
MicroArchitecture.ElkhartLake or
MicroArchitecture.Tremont)
{
@@ -630,7 +631,7 @@ internal sealed class IntelCpu : GenericCpu
case MicroArchitecture.Silvermont:
case MicroArchitecture.Skylake:
case MicroArchitecture.TigerLake:
case MicroArchitecture.SapphireRapids:
case MicroArchitecture.SapphireRapids:
case MicroArchitecture.ElkhartLake:
case MicroArchitecture.Tremont:
_coreClocks[i].Value = (float)(((eax >> 8) & 0xff) * newBusClock);
@@ -724,7 +725,7 @@ internal sealed class IntelCpu : GenericCpu
TigerLake,
Tremont,
RaptorLake,
SapphireRapids,
SapphireRapids,
ElkhartLake,
Unknown
}