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Intel Arrow Lake 200 added (#1495)

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This commit is contained in:
Markus H.
2024-10-17 12:44:53 +02:00
committed by GitHub
parent 0a7f8df282
commit 0c32773dc2
1 changed files with 13 additions and 5 deletions
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LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
+13 -5
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@@ -220,8 +220,13 @@ internal sealed class IntelCpu : GenericCpu
case 0xA7: // Intel Core i5, i6, i7 11xxx (14nm) (Rocket Lake)
_microArchitecture = MicroArchitecture.RocketLake;
tjMax = GetTjMaxFromMsr();
break;
break;
case 0xC6: // Intel Core Ultra 7 200 Series ArrowLake
_microArchitecture = MicroArchitecture.ArrowLake;
tjMax = GetTjMaxFromMsr();
break;
default:
_microArchitecture = MicroArchitecture.Unknown;
tjMax = Floats(100);
@@ -267,7 +272,8 @@ internal sealed class IntelCpu : GenericCpu
break;
case MicroArchitecture.Airmont:
case MicroArchitecture.AlderLake:
case MicroArchitecture.AlderLake:
case MicroArchitecture.ArrowLake:
case MicroArchitecture.Broadwell:
case MicroArchitecture.CannonLake:
case MicroArchitecture.CometLake:
@@ -381,7 +387,8 @@ internal sealed class IntelCpu : GenericCpu
}
if (_microArchitecture is MicroArchitecture.Airmont or
MicroArchitecture.AlderLake or
MicroArchitecture.AlderLake or
MicroArchitecture.ArrowLake or
MicroArchitecture.Broadwell or
MicroArchitecture.CannonLake or
MicroArchitecture.CometLake or
@@ -584,6 +591,7 @@ internal sealed class IntelCpu : GenericCpu
break;
case MicroArchitecture.Airmont:
case MicroArchitecture.AlderLake:
case MicroArchitecture.ArrowLake:
case MicroArchitecture.Broadwell:
case MicroArchitecture.CannonLake:
case MicroArchitecture.CometLake:
@@ -601,7 +609,7 @@ internal sealed class IntelCpu : GenericCpu
case MicroArchitecture.Silvermont:
case MicroArchitecture.Skylake:
case MicroArchitecture.TigerLake:
case MicroArchitecture.Tremont:
case MicroArchitecture.Tremont:
_coreClocks[i].Value = (float)(((eax >> 8) & 0xff) * newBusClock);
break;
default: