JMR-dev/ReLibreHardwareMonitor
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 1 Wiki Activity
1,153 Commits 1 Branch 1 Tag
1ca4ebca9589fe6f23bc6dfefced51005d29e9d3
Commit Graph
51 Commits
Author SHA1 Message Date
Howon Lee cc303f75c5 Added support for Lunar Lake CPUs (#1520) 
* Added support for Lunar Lake CPUs

* Fixed a typo
 2024-11-12 18:45:16 +01:00
Markus H. 0c32773dc2 Intel Arrow Lake 200 added (#1495) 2024-10-17 12:44:53 +02:00
sebastian-devandPhyxionNL 23207acb09 Support Ryzen 9000 Series (#1469) 
* Support Ryzen 9000 Series
https://github.com/LibreHardwareMonitor/LibreHardwareMonitor/issues/1467
https://github.com/LibreHardwareMonitor/LibreHardwareMonitor/issues/1418

* Update Amd17Cpu.cs

* Update Amd17Cpu.cs

---------

Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2024-09-20 10:21:21 +02:00
PhyxionNL edf2a9a325 Add name replacing from #1297 2024-08-23 15:49:37 +02:00
SeongChan LeeandPhyxionNL 65058eb1f7 Add MSR_PLATFORM_ENERGY_COUNTER 0x64D (#1357) 
* Add MSR_PLATFORM_ENERGY_COUNTER (0x64D)

MSR_PLATFORM_ENERGY_COUNTER 0x64D is a platform energy counter register according to
p. 2-272, "Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4: Model-Specific Registers"
It's description is:
> Total energy consumed by all devices in the platform
> that receive power from integrated power delivery
> mechanism, included platform devices are processor
> cores, SOC, memory, add-on or peripheral devices that
> get powered directly from the platform power delivery
> means. The energy units are specified in the
> MSR_RAPL_POWER_UNIT.Enery_Status_Unit.

* Update IntelCpu.cs

---------

Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2024-06-11 16:30:53 +02:00
sebastian-devandPhyxionNL dd5b3e1610 Intel Gen 14 Meteor Lake (#1253) 
* Intel Gen 14 Meteor Lake
New Intel Gen.14 CPU Model ID

* Update IntelCpu.cs

---------

Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2024-01-29 11:48:35 +01:00
PhyxionNL c0f2740ed3 Move mutexes out of Ring0 2023-06-14 11:58:26 +02:00
Matt Lichter eff66283e6 Create virtual sensor for maximum CPU load across all cores. (#1047) 2023-04-11 11:19:36 +02:00
PhyxionNL cd77cec0b5 Unify CPU namespace with folder (#1023) 2023-03-21 18:11:40 +01:00
javs 297c3485d6 Add support for Gigabyte's custom fan controller (#1020) 2023-03-21 17:55:15 +01:00
asrulhadi d901c079b7 Linux cpu load (#981) 2023-03-16 10:28:47 +01:00
PhyxionNL 64e38a4d40 Cleanup thread affinity and support > 64 threads. 2023-03-14 17:01:03 +01:00
Arnold Vink 6a1a28a893 Fix for Windows 11 22H2 (22621) incorrect total CPU load issue. (#933) 
* Fix for Windows 11 22H2 (22621) incorrect total CPU load issue.

* Fix for Windows 11 22H2 (22621) incorrect total CPU load issue.
 2022-12-19 18:55:10 +01:00
sebastian-devandPhyxionNL fe326e8877 Zen 4 SMU Update (#915) 
* Zen 4 SMU Update

* Misc

Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2022-12-01 10:52:10 +01:00
PhyxionNL 58cef111a1 Use file-scoped namespaces (#842) 2022-10-09 13:22:57 +02:00
PhyxionNL 3ac329f247 Fix some code analysis issues (#841) 2022-10-09 13:16:31 +02:00
PhyxionNL a6f28dc7e6 Add RaptorLake and one more Alder Lake (#815) 2022-09-14 12:14:46 +02:00
DevTechProfile e9e8e034ef Added Alder Lake-H model ID (#779) 2022-07-15 10:09:26 +02:00
PhyxionNL 38b97e10d0 Update editorconfig + changes (#771) 2022-06-29 19:38:57 +02:00
EMN-CSharp eed7742e7e Add support for VID sensors per core on Intel CPUs (#741) 
* Add support for VID sensors per core on Intel CPUs

* Remove pointless variable assignment
 2022-05-12 09:57:08 +02:00
Bjarni Ivarsson e68fd4e8ef "CPU Core" voltage sensor for intel CPU's (#682) 
* first attempt

* review updates
 2022-03-01 09:59:41 +01:00
Bjarni Ivarsson 7de86a4f5e Per-thread cpu load (#673) 
Thanks to @bjarniivarsson.
 2022-02-26 10:19:17 +01:00
Bjarni Ivarsson 627f0a56ce Add Intel integrated GPU (#671) 
Thanks to @bjarniivarsson.
 2022-02-26 10:14:09 +01:00
PhyxionNL 23f515612c Add Alder Lake and Jasper Lake (#589) 
Fixes #588
 2021-11-03 10:49:50 +01:00
PhyxionNL f157563c33 Expose CPU index. 2021-10-22 15:30:16 +02:00
kolos 3df898af24 Add Ryzen SMU support (#428) 
Thanks to @kolos.
 2021-06-11 09:36:17 +02:00
kolos d14557fdea Enable reporting SoC voltage for Zen+ APUs (#424) 2021-04-11 13:55:58 +02:00
sebastian-dev ab6a89ea3f Intel Gen11 Rocket Lake Support (#421) 
Thanks to @sebastian-dev
 2021-04-09 10:45:40 +02:00
PhyxionNL 4b12fed029 Update Amd17Cpu.cs 
Clean up comments a bit.
 2021-02-08 10:51:40 +01:00
sebastian-dev 46150305f2 AMD Ryzen, wrong CPU Core Enumeration (#376) 
Thanks to @sebastian-dev
 2021-02-08 10:50:06 +01:00
PhyxionNL ea484f5c55 Use bus speed on AMD's Ryzen CPUs 
Fixes #329.
 2020-11-20 10:07:58 +01:00
Lucas Towers a80b455eaa Add support for AMD Ryzen 5000 processors (#328) 
* Add bare-minimum support for family 0x19

* Treat Zen 3 like Zen 2 in most-cases

* Remove mistakenly added whitespace
 2020-11-14 20:16:51 +01:00
sebastian-dev 22858791e9 Bugfix: AMD 39xx CCD Temperatures (#289) 2020-08-11 09:22:28 +02:00
Phyxion 5d7f476711 Fixes #266 
Groups must be locked during reset, otherwise the collection can be modified while enumerating.
 2020-07-17 09:48:35 +02:00
sebastian-dev 0eaedcbbd6 AMD17, Bus Clock and Core 1 has the same Hardware id (#264) 2020-05-29 11:34:52 +02:00
sebastian-dev 7dd2af97bf Add Mutex release in Amd17. 
Thanks to @sebastian-dev
 2020-05-27 11:16:27 +02:00
Phyxion b118b7a2f1 Add support for Global\\Access_PCI mutex 
Based on the work of @moellerm
 2020-05-25 12:04:28 +02:00
Phyxion fe662558f4 Added experimental support for Intel 06_A5h CPUs 
Thanks to @moellerm.
 2020-05-25 11:28:45 +02:00
Phyxion 3cc3d9139c Add support for multiple processor groups. 
Merge from upstream.
 2020-05-11 13:29:52 +02:00
Phyxion ec01af6cd0 Update Amd17Cpu.cs 
Fixes #237
 2020-05-03 22:29:01 +02:00
Phyxion 42e6a3eb19 Add support for Intel Comet Lake 
Also add CORS header for https://github.com/openhardwaremonitor/openhardwaremonitor/issues/1234
 2020-03-02 17:14:00 +01:00
Phyxion 5bd108167d Restore OHM in copyright statement 2020-02-28 11:39:25 +01:00
Phyxion 9a9d670ca7 Update from upstream 2020-02-26 10:58:56 +01:00
Phyxion 2c44ddd7f4 Partially addresses #200 2020-01-28 16:43:43 +01:00
PhyxionandRaINi_ f7278652b5 Add Zen 2 CCD temperatures and merged Tdie/Tctl. 
Based on the work of @LeagueRaINi

Co-Authored-By: RaINi_ <razor13372k@gmail.com>
 2020-01-17 12:10:15 +01:00
Nick Babcock f4fb5ad13b Fix source file names on case sensitive file systems (#192) 
Source file names will now match the class names.
 2020-01-06 10:24:18 +01:00
Phyxion d26dcc4189 Update Ryzen temperature offsets 
Fixes #176
 2019-12-13 14:58:03 +01:00
RaINi_ 95fdd4920d Add SoC voltage for Ryzen 2 
Thanks to @LeagueRaINi
 2019-12-13 14:40:56 +01:00
Stefan Hirschmann 404b2a766b Add support for Intel Goldmont, Goldmont Plus, Cannon Lake, Ice Lake, Tiger Lake and Tremont microarchitectures (#170) 
Thanks to @hirschmann
 2019-11-21 14:34:46 +01:00
Phyxion 059b43cc14 Unify remaining memory names 2019-10-11 12:39:56 +02:00