 asrulhadi
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d901c079b7
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Linux cpu load (#981)
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2023-03-16 10:28:47 +01:00 |
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PhyxionNL
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64e38a4d40
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Cleanup thread affinity and support > 64 threads.
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2023-03-14 17:01:03 +01:00 |
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Arnold Vink
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6a1a28a893
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Fix for Windows 11 22H2 (22621) incorrect total CPU load issue. (#933)
* Fix for Windows 11 22H2 (22621) incorrect total CPU load issue.
* Fix for Windows 11 22H2 (22621) incorrect total CPU load issue.
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2022-12-19 18:55:10 +01:00 |
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sebastian-devandPhyxionNL
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fe326e8877
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Zen 4 SMU Update (#915)
* Zen 4 SMU Update
* Misc
Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
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2022-12-01 10:52:10 +01:00 |
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PhyxionNL
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58cef111a1
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Use file-scoped namespaces (#842)
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2022-10-09 13:22:57 +02:00 |
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PhyxionNL
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3ac329f247
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Fix some code analysis issues (#841)
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2022-10-09 13:16:31 +02:00 |
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PhyxionNL
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a6f28dc7e6
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Add RaptorLake and one more Alder Lake (#815)
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2022-09-14 12:14:46 +02:00 |
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DevTechProfile
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e9e8e034ef
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Added Alder Lake-H model ID (#779)
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2022-07-15 10:09:26 +02:00 |
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PhyxionNL
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38b97e10d0
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Update editorconfig + changes (#771)
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2022-06-29 19:38:57 +02:00 |
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EMN-CSharp
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eed7742e7e
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Add support for VID sensors per core on Intel CPUs (#741)
* Add support for VID sensors per core on Intel CPUs
* Remove pointless variable assignment
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2022-05-12 09:57:08 +02:00 |
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Bjarni Ivarsson
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e68fd4e8ef
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"CPU Core" voltage sensor for intel CPU's (#682)
* first attempt
* review updates
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2022-03-01 09:59:41 +01:00 |
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Bjarni Ivarsson
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7de86a4f5e
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Per-thread cpu load (#673)
Thanks to @bjarniivarsson.
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2022-02-26 10:19:17 +01:00 |
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Bjarni Ivarsson
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627f0a56ce
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Add Intel integrated GPU (#671)
Thanks to @bjarniivarsson.
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2022-02-26 10:14:09 +01:00 |
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PhyxionNL
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23f515612c
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Add Alder Lake and Jasper Lake (#589)
Fixes #588
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2021-11-03 10:49:50 +01:00 |
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PhyxionNL
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f157563c33
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Expose CPU index.
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2021-10-22 15:30:16 +02:00 |
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kolos
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3df898af24
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Add Ryzen SMU support (#428)
Thanks to @kolos.
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2021-06-11 09:36:17 +02:00 |
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kolos
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d14557fdea
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Enable reporting SoC voltage for Zen+ APUs (#424)
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2021-04-11 13:55:58 +02:00 |
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sebastian-dev
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ab6a89ea3f
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Intel Gen11 Rocket Lake Support (#421)
Thanks to @sebastian-dev
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2021-04-09 10:45:40 +02:00 |
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PhyxionNL
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4b12fed029
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Update Amd17Cpu.cs
Clean up comments a bit.
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2021-02-08 10:51:40 +01:00 |
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sebastian-dev
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46150305f2
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AMD Ryzen, wrong CPU Core Enumeration (#376)
Thanks to @sebastian-dev
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2021-02-08 10:50:06 +01:00 |
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PhyxionNL
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ea484f5c55
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Use bus speed on AMD's Ryzen CPUs
Fixes #329.
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2020-11-20 10:07:58 +01:00 |
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Lucas Towers
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a80b455eaa
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Add support for AMD Ryzen 5000 processors (#328)
* Add bare-minimum support for family 0x19
* Treat Zen 3 like Zen 2 in most-cases
* Remove mistakenly added whitespace
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2020-11-14 20:16:51 +01:00 |
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sebastian-dev
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22858791e9
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Bugfix: AMD 39xx CCD Temperatures (#289)
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2020-08-11 09:22:28 +02:00 |
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Phyxion
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5d7f476711
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Fixes #266
Groups must be locked during reset, otherwise the collection can be modified while enumerating.
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2020-07-17 09:48:35 +02:00 |
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sebastian-dev
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0eaedcbbd6
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AMD17, Bus Clock and Core 1 has the same Hardware id (#264)
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2020-05-29 11:34:52 +02:00 |
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sebastian-dev
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7dd2af97bf
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Add Mutex release in Amd17.
Thanks to @sebastian-dev
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2020-05-27 11:16:27 +02:00 |
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Phyxion
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b118b7a2f1
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Add support for Global\\Access_PCI mutex
Based on the work of @moellerm
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2020-05-25 12:04:28 +02:00 |
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Phyxion
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fe662558f4
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Added experimental support for Intel 06_A5h CPUs
Thanks to @moellerm.
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2020-05-25 11:28:45 +02:00 |
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Phyxion
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3cc3d9139c
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Add support for multiple processor groups.
Merge from upstream.
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2020-05-11 13:29:52 +02:00 |
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Phyxion
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ec01af6cd0
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Update Amd17Cpu.cs
Fixes #237
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2020-05-03 22:29:01 +02:00 |
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Phyxion
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42e6a3eb19
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Add support for Intel Comet Lake
Also add CORS header for https://github.com/openhardwaremonitor/openhardwaremonitor/issues/1234
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2020-03-02 17:14:00 +01:00 |
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Phyxion
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5bd108167d
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Restore OHM in copyright statement
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2020-02-28 11:39:25 +01:00 |
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Phyxion
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9a9d670ca7
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Update from upstream
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2020-02-26 10:58:56 +01:00 |
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Phyxion
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2c44ddd7f4
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Partially addresses #200
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2020-01-28 16:43:43 +01:00 |
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PhyxionandRaINi_
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f7278652b5
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Add Zen 2 CCD temperatures and merged Tdie/Tctl.
Based on the work of @LeagueRaINi
Co-Authored-By: RaINi_ <razor13372k@gmail.com>
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2020-01-17 12:10:15 +01:00 |
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Nick Babcock
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f4fb5ad13b
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Fix source file names on case sensitive file systems (#192)
Source file names will now match the class names.
|
2020-01-06 10:24:18 +01:00 |
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Phyxion
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d26dcc4189
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Update Ryzen temperature offsets
Fixes #176
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2019-12-13 14:58:03 +01:00 |
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RaINi_
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95fdd4920d
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Add SoC voltage for Ryzen 2
Thanks to @LeagueRaINi
|
2019-12-13 14:40:56 +01:00 |
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Stefan Hirschmann
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404b2a766b
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Add support for Intel Goldmont, Goldmont Plus, Cannon Lake, Ice Lake, Tiger Lake and Tremont microarchitectures (#170)
Thanks to @hirschmann
|
2019-11-21 14:34:46 +01:00 |
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Phyxion
|
059b43cc14
|
Unify remaining memory names
|
2019-10-11 12:39:56 +02:00 |
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Phyxion
|
73378f7c7b
|
Code style #130 (#132)
This closes #99.
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2019-09-23 19:29:10 +02:00 |
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