 Lucas Towers
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a80b455eaa
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Add support for AMD Ryzen 5000 processors (#328)
* Add bare-minimum support for family 0x19
* Treat Zen 3 like Zen 2 in most-cases
* Remove mistakenly added whitespace
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2020-11-14 20:16:51 +01:00 |
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sebastian-dev
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22858791e9
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Bugfix: AMD 39xx CCD Temperatures (#289)
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2020-08-11 09:22:28 +02:00 |
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Phyxion
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5d7f476711
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Fixes #266
Groups must be locked during reset, otherwise the collection can be modified while enumerating.
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2020-07-17 09:48:35 +02:00 |
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sebastian-dev
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0eaedcbbd6
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AMD17, Bus Clock and Core 1 has the same Hardware id (#264)
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2020-05-29 11:34:52 +02:00 |
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sebastian-dev
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7dd2af97bf
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Add Mutex release in Amd17.
Thanks to @sebastian-dev
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2020-05-27 11:16:27 +02:00 |
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Phyxion
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b118b7a2f1
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Add support for Global\\Access_PCI mutex
Based on the work of @moellerm
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2020-05-25 12:04:28 +02:00 |
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Phyxion
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fe662558f4
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Added experimental support for Intel 06_A5h CPUs
Thanks to @moellerm.
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2020-05-25 11:28:45 +02:00 |
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Phyxion
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3cc3d9139c
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Add support for multiple processor groups.
Merge from upstream.
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2020-05-11 13:29:52 +02:00 |
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Phyxion
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ec01af6cd0
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Update Amd17Cpu.cs
Fixes #237
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2020-05-03 22:29:01 +02:00 |
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Phyxion
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42e6a3eb19
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Add support for Intel Comet Lake
Also add CORS header for https://github.com/openhardwaremonitor/openhardwaremonitor/issues/1234
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2020-03-02 17:14:00 +01:00 |
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Phyxion
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5bd108167d
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Restore OHM in copyright statement
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2020-02-28 11:39:25 +01:00 |
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Phyxion
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9a9d670ca7
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Update from upstream
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2020-02-26 10:58:56 +01:00 |
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Phyxion
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2c44ddd7f4
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Partially addresses #200
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2020-01-28 16:43:43 +01:00 |
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PhyxionandRaINi_
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f7278652b5
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Add Zen 2 CCD temperatures and merged Tdie/Tctl.
Based on the work of @LeagueRaINi
Co-Authored-By: RaINi_ <razor13372k@gmail.com>
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2020-01-17 12:10:15 +01:00 |
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Nick Babcock
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f4fb5ad13b
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Fix source file names on case sensitive file systems (#192)
Source file names will now match the class names.
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2020-01-06 10:24:18 +01:00 |
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Phyxion
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d26dcc4189
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Update Ryzen temperature offsets
Fixes #176
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2019-12-13 14:58:03 +01:00 |
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RaINi_
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95fdd4920d
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Add SoC voltage for Ryzen 2
Thanks to @LeagueRaINi
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2019-12-13 14:40:56 +01:00 |
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Stefan Hirschmann
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404b2a766b
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Add support for Intel Goldmont, Goldmont Plus, Cannon Lake, Ice Lake, Tiger Lake and Tremont microarchitectures (#170)
Thanks to @hirschmann
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2019-11-21 14:34:46 +01:00 |
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Phyxion
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059b43cc14
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Unify remaining memory names
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2019-10-11 12:39:56 +02:00 |
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Phyxion
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73378f7c7b
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Code style #130 (#132)
This closes #99.
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2019-09-23 19:29:10 +02:00 |
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