3 Commits

Include renames

Author	SHA1	Message	Date
Stefan Hirschmann	404b2a766b	Add support for Intel Goldmont, Goldmont Plus, Cannon Lake, Ice Lake, Tiger Lake and Tremont microarchitectures (#170) ... Thanks to @hirschmann	2019-11-21 14:34:46 +01:00
Phyxion	059b43cc14	Unify remaining memory names	2019-10-11 12:39:56 +02:00
Phyxion	73378f7c7b	Code style #130 (#132) ... This closes #99.	2019-09-23 19:29:10 +02:00