 PhyxionandRaINi_
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f7278652b5
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Add Zen 2 CCD temperatures and merged Tdie/Tctl.
Based on the work of @LeagueRaINi
Co-Authored-By: RaINi_ <razor13372k@gmail.com>
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2020-01-17 12:10:15 +01:00 |
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Nick Babcock
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f4fb5ad13b
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Fix source file names on case sensitive file systems (#192)
Source file names will now match the class names.
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2020-01-06 10:24:18 +01:00 |
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Phyxion
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d26dcc4189
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Update Ryzen temperature offsets
Fixes #176
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2019-12-13 14:58:03 +01:00 |
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RaINi_
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95fdd4920d
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Add SoC voltage for Ryzen 2
Thanks to @LeagueRaINi
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2019-12-13 14:40:56 +01:00 |
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Stefan Hirschmann
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404b2a766b
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Add support for Intel Goldmont, Goldmont Plus, Cannon Lake, Ice Lake, Tiger Lake and Tremont microarchitectures (#170)
Thanks to @hirschmann
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2019-11-21 14:34:46 +01:00 |
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Phyxion
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059b43cc14
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Unify remaining memory names
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2019-10-11 12:39:56 +02:00 |
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Phyxion
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73378f7c7b
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Code style #130 (#132)
This closes #99.
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2019-09-23 19:29:10 +02:00 |
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