sebastian-dev and PhyxionNL
342c4f5f52
Ryzen 9000 Core Frequency Bugfix ( #1548 )
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* Ryzen 9000 Core Frequency Bugfix
Zen5 (Ryzen 9000) has a changed register mapping for readout core frequency
* Update Ryzen 9000 and Core Clock
* fixed Package Power and Core power Calculation, use ESU for power scaling
* Changed DateTime.Now to UtcNow (better performance)
* Added Effective core clock
* Added Average Core clock and Average effective clock
* Remove Effective clock from SMU
Core effective clock is now calculated in Amd17Cpu/Core
* Fix Clock Ratio calculation.
Ratio > 1 is not possible
* Update Amd17Cpu.cs
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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com >
2025-02-04 16:43:51 +01:00
sebastian-dev and PhyxionNL
23207acb09
Support Ryzen 9000 Series ( #1469 )
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* Support Ryzen 9000 Series
https://github.com/LibreHardwareMonitor/LibreHardwareMonitor/issues/1467
https://github.com/LibreHardwareMonitor/LibreHardwareMonitor/issues/1418
* Update Amd17Cpu.cs
* Update Amd17Cpu.cs
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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com >
2024-09-20 10:21:21 +02:00
PhyxionNL
717ba8e22f
Fixes #1346
2024-08-23 16:25:27 +02:00
namazso
e6b8c42c15
Add table size for version 0x540104 ( #1099 )
2023-06-16 14:25:43 +02:00
PhyxionNL
c0f2740ed3
Move mutexes out of Ring0
2023-06-14 11:58:26 +02:00
PhyxionNL
20bf5bb1f7
Check if ADL overdrive caps method exists and InpOut opened OK.
2023-03-14 17:29:28 +01:00
sebastian-dev and PhyxionNL
fe326e8877
Zen 4 SMU Update ( #915 )
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* Zen 4 SMU Update
* Misc
Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com >
2022-12-01 10:52:10 +01:00
PhyxionNL
58cef111a1
Use file-scoped namespaces ( #842 )
2022-10-09 13:22:57 +02:00
PhyxionNL
3ac329f247
Fix some code analysis issues ( #841 )
2022-10-09 13:16:31 +02:00
PhyxionNL
38b97e10d0
Update editorconfig + changes ( #771 )
2022-06-29 19:38:57 +02:00
K900
4b0bf583e1
RyzenSMU: add some more metrics for Zen3 ( #750 )
2022-06-03 17:19:20 +02:00
PhyxionNL
0ed564e7c6
Zen 3 smu ( #652 )
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Thanks to @DevTechProfile
2022-02-07 16:59:03 +01:00
PhyxionNL
65664fd75e
Update RyzenSMU.cs
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Fixes #613 .
2022-01-13 10:20:06 +01:00
PhyxionNL
9bf2447ab9
https://github.com/LibreHardwareMonitor/LibreHardwareMonitor/issues/566#issuecomment-944841060
2021-10-16 10:34:05 +02:00
PhyxionNL
1cd403a6fa
If running under 32-bit mode, the DRAM table cannot be read as it's overflowing
2021-09-29 11:44:50 +02:00
PhyxionNL
a10c33ec0a
WinRing0 revert ( #478 )
2021-06-21 18:30:21 +02:00
kolos
57140e219b
Fix AMD sensor index for RR ( #470 )
2021-06-14 18:12:05 +02:00
kolos
3df898af24
Add Ryzen SMU support ( #428 )
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Thanks to @kolos.
2021-06-11 09:36:17 +02:00
