This commit is contained in:
PhyxionNL
2024-08-23 16:25:27 +02:00
parent 4f09a80f78
commit 717ba8e22f
+23 -27
View File
@@ -18,7 +18,6 @@ internal class RyzenSMU
private const uint SMU_RETRIES_MAX = 8096;
private readonly CpuCodeName _cpuCodeName;
private readonly Mutex _mutex = new();
private readonly bool _supportedCPU;
private readonly Dictionary<uint, Dictionary<uint, SmuSensorType>> _supportedPmTableVersions = new()
@@ -264,12 +263,9 @@ internal class RyzenSMU
public uint GetSmuVersion()
{
uint[] args = { 1 };
uint[] args = [1];
if (SendCommand(0x02, ref args))
return args[0];
return 0;
return SendCommand(0x02, ref args) ? args[0] : 0;
}
public Dictionary<uint, SmuSensorType> GetPmTableStructure()
@@ -288,7 +284,7 @@ internal class RyzenSMU
public float[] GetPmTable()
{
if (!_supportedCPU || !TransferTableToDram())
return new float[] { 0 };
return [0];
float[] table = ReadDramToArray();
@@ -451,7 +447,7 @@ internal class RyzenSMU
private bool GetPmTableVersion(ref uint version)
{
uint[] args = { 0 };
uint[] args = [0];
uint fn;
switch (_cpuCodeName)
@@ -482,7 +478,7 @@ internal class RyzenSMU
private void SetupAddrClass1(uint[] fn)
{
uint[] args = { 1, 1 };
uint[] args = [1, 1];
bool command = SendCommand(fn[0], ref args);
if (!command)
@@ -494,13 +490,13 @@ internal class RyzenSMU
private void SetupAddrClass2(uint[] fn)
{
uint[] args = { 0, 0, 0, 0, 0, 0 };
uint[] args = [0, 0, 0, 0, 0, 0];
bool command = SendCommand(fn[0], ref args);
if (!command)
return;
args = new uint[] { 0 };
args = [0];
command = SendCommand(fn[1], ref args);
if (!command)
return;
@@ -510,15 +506,15 @@ internal class RyzenSMU
private void SetupAddrClass3(uint[] fn)
{
uint[] parts = { 0, 0 };
uint[] parts = [0, 0];
// == Part 1 ==
uint[] args = { 3 };
uint[] args = [3];
bool command = SendCommand(fn[0], ref args);
if (!command)
return;
args = new uint[] { 3 };
args = [3];
command = SendCommand(fn[2], ref args);
if (!command)
return;
@@ -528,17 +524,17 @@ internal class RyzenSMU
// == Part 1 End ==
// == Part 2 ==
args = new uint[] { 3 };
args = [3];
command = SendCommand(fn[1], ref args);
if (!command)
return;
args = new uint[] { 5 };
args = [5];
command = SendCommand(fn[0], ref args);
if (!command)
return;
args = new uint[] { 5 };
args = [5];
command = SendCommand(fn[2], ref args);
if (!command)
return;
@@ -552,7 +548,7 @@ internal class RyzenSMU
private void SetupDramBaseAddr()
{
uint[] fn = { 0, 0, 0 };
uint[] fn = [0, 0, 0];
switch (_cpuCodeName)
{
@@ -592,7 +588,7 @@ internal class RyzenSMU
public bool TransferTableToDram()
{
uint[] args = { 0 };
uint[] args = [0];
uint fn;
switch (_cpuCodeName)
@@ -630,7 +626,7 @@ internal class RyzenSMU
cmdArgs[i] = args[i];
uint tmp = 0;
if (_mutex.WaitOne(5000))
if (Mutexes.WaitPciBus(5000))
{
// Step 1: Wait until the RSP register is non-zero.
@@ -640,17 +636,17 @@ internal class RyzenSMU
{
if (!ReadReg(_rspAddr, ref tmp))
{
_mutex.ReleaseMutex();
Mutexes.ReleasePciBus();
return false;
}
}
while (tmp == 0 && 0 != retries--);
while (tmp == 0 && retries-- != 0);
// Step 1.b: A command is still being processed meaning a new command cannot be issued.
if (retries == 0 && tmp == 0)
{
_mutex.ReleaseMutex();
Mutexes.ReleasePciBus();
return false;
}
@@ -671,7 +667,7 @@ internal class RyzenSMU
{
if (!ReadReg(_rspAddr, ref tmp))
{
_mutex.ReleaseMutex();
Mutexes.ReleasePciBus();
return false;
}
}
@@ -679,7 +675,7 @@ internal class RyzenSMU
if (retries == 0 && tmp != (uint)Status.OK)
{
_mutex.ReleaseMutex();
Mutexes.ReleasePciBus();
return false;
}
@@ -690,13 +686,13 @@ internal class RyzenSMU
{
if (!ReadReg(_argsAddr + (uint)(i * 4), ref args[i]))
{
_mutex.ReleaseMutex();
Mutexes.ReleasePciBus();
return false;
}
}
ReadReg(_rspAddr, ref tmp);
_mutex.ReleaseMutex();
Mutexes.ReleasePciBus();
}
return tmp == (uint)Status.OK;