From a6f28dc7e6b7fd8333d7257bf86ab21d0829beda Mon Sep 17 00:00:00 2001
From: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
Date: Wed, 14 Sep 2022 12:14:46 +0200
Subject: [PATCH] Add RaptorLake and one more Alder Lake (#815)

---
 LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
index 05e7e0c..6ab218a 100644
--- a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
+++ b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
@@ -193,10 +193,18 @@ namespace LibreHardwareMonitor.Hardware.CPU
                                 tjMax = GetTjMaxFromMsr();
                                 break;
 
-                            case 0x97: // Alder Lake-S (Intel 7/10nm)
-                            case 0x9A: // Alder Lake-H (Intel 7/10nm)
+                            case 0x97: // Alder Lake (7/10nm)
+                            case 0x9A: // Alder Lake-L (7/10nm)
+                            case 0xBE: // Alder Lake-N (7/10nm)
                                 _microArchitecture = MicroArchitecture.AlderLake;
                                 tjMax = GetTjMaxFromMsr();
+                                break;
+
+							case 0xB7: // Raptor Lake (7nm)
+							case 0xBA: // Raptor Lake-P (7nm)
+							case 0xBF: // Raptor Lake-N (7nm)
+                                _microArchitecture = MicroArchitecture.RaptorLake;
+                                tjMax = GetTjMaxFromMsr();
                                 break;
 
                             case 0x9C: // Jasper Lake (10nm)
@@ -266,6 +274,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
                 case MicroArchitecture.JasperLake:
                 case MicroArchitecture.KabyLake:
                 case MicroArchitecture.Nehalem:
+                case MicroArchitecture.RaptorLake:
                 case MicroArchitecture.RocketLake:
                 case MicroArchitecture.SandyBridge:
                 case MicroArchitecture.Silvermont:
@@ -377,6 +386,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
                 MicroArchitecture.IvyBridge or
                 MicroArchitecture.JasperLake or
                 MicroArchitecture.KabyLake or
+                MicroArchitecture.RaptorLake or
                 MicroArchitecture.RocketLake or
                 MicroArchitecture.SandyBridge or
                 MicroArchitecture.Silvermont or
@@ -577,6 +587,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
                             case MicroArchitecture.IvyBridge:
                             case MicroArchitecture.JasperLake:
                             case MicroArchitecture.KabyLake:
+                            case MicroArchitecture.RaptorLake:
                             case MicroArchitecture.RocketLake:
                             case MicroArchitecture.SandyBridge:
                             case MicroArchitecture.Silvermont:
@@ -670,6 +681,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
             Skylake,
             TigerLake,
             Tremont,
+            RaptorLake,
             Unknown
         }