From 0c32773dc21f65beff5c3d7bac92e12625da7968 Mon Sep 17 00:00:00 2001
From: "Markus H." <57905025+MaHoBo@users.noreply.github.com>
Date: Thu, 17 Oct 2024 12:44:53 +0200
Subject: [PATCH] Intel Arrow Lake 200 added (#1495)

---
 .../Hardware/Cpu/IntelCpu.cs                   | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
index 5e63b8a..f8766d8 100644
--- a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
+++ b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
@@ -220,8 +220,13 @@ internal sealed class IntelCpu : GenericCpu
                         case 0xA7: // Intel Core i5, i6, i7 11xxx (14nm) (Rocket Lake)
                             _microArchitecture = MicroArchitecture.RocketLake;
                             tjMax = GetTjMaxFromMsr();
-                            break;
-
+                            break;
+
+                        case 0xC6: // Intel Core Ultra 7 200 Series ArrowLake
+                            _microArchitecture = MicroArchitecture.ArrowLake;
+                            tjMax = GetTjMaxFromMsr();
+                            break;
+
                         default:
                             _microArchitecture = MicroArchitecture.Unknown;
                             tjMax = Floats(100);
@@ -267,7 +272,8 @@ internal sealed class IntelCpu : GenericCpu
 
                 break;
             case MicroArchitecture.Airmont:
-            case MicroArchitecture.AlderLake:
+            case MicroArchitecture.AlderLake:
+            case MicroArchitecture.ArrowLake:
             case MicroArchitecture.Broadwell:
             case MicroArchitecture.CannonLake:
             case MicroArchitecture.CometLake:
@@ -381,7 +387,8 @@ internal sealed class IntelCpu : GenericCpu
         }
 
         if (_microArchitecture is MicroArchitecture.Airmont or
-            MicroArchitecture.AlderLake or
+            MicroArchitecture.AlderLake or
+            MicroArchitecture.ArrowLake or
             MicroArchitecture.Broadwell or
             MicroArchitecture.CannonLake or
             MicroArchitecture.CometLake or
@@ -584,6 +591,7 @@ internal sealed class IntelCpu : GenericCpu
                             break;
                         case MicroArchitecture.Airmont:
                         case MicroArchitecture.AlderLake:
+                        case MicroArchitecture.ArrowLake:
                         case MicroArchitecture.Broadwell:
                         case MicroArchitecture.CannonLake:
                         case MicroArchitecture.CometLake:
@@ -601,7 +609,7 @@ internal sealed class IntelCpu : GenericCpu
                         case MicroArchitecture.Silvermont:
                         case MicroArchitecture.Skylake:
                         case MicroArchitecture.TigerLake:
-                        case MicroArchitecture.Tremont:
+                        case MicroArchitecture.Tremont:
                             _coreClocks[i].Value = (float)(((eax >> 8) & 0xff) * newBusClock);
                             break;
                         default: