JMR-dev/ReLibreHardwareMonitor
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 1 Wiki Activity
1,299 Commits 1 Branch 1 Tag
d358e1fc7a2cd940b5c3b58dfd896f3e4cff57fd
Commit Graph
27 Commits
Author SHA1 Message Date
namazsoandPhyxionNL eb5e1a20be Swap WinRing0 to PawnIO (#1857) 
* Replace WinRing0 with PawnIO

* Update RAMSPDToolkit

* Add install check + cleanup

* Move folder + formatting

* Add back missing TryLoadDll

* Update PawnIo.cs

* Add third party notices file

* Remove the how to apply section

* Drop silent

* Don't crash if PawnIO isn't installed

* Formatting

---------

Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2025-09-16 11:58:31 +02:00
sebastian-devandPhyxionNL 342c4f5f52 Ryzen 9000 Core Frequency Bugfix (#1548) 
* Ryzen 9000 Core Frequency Bugfix
Zen5 (Ryzen 9000) has a changed register mapping for readout core frequency

* Update Ryzen 9000 and Core Clock
* fixed Package Power and Core power Calculation, use ESU for power scaling
* Changed DateTime.Now to UtcNow (better performance)
* Added Effective core clock
* Added Average Core clock and Average effective clock

* Remove Effective clock from SMU
Core effective clock is now calculated in Amd17Cpu/Core

* Fix Clock Ratio calculation.
Ratio > 1 is not possible

* Update Amd17Cpu.cs

---------

Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2025-02-04 16:43:51 +01:00
sebastian-devandPhyxionNL 23207acb09 Support Ryzen 9000 Series (#1469) 
* Support Ryzen 9000 Series
https://github.com/LibreHardwareMonitor/LibreHardwareMonitor/issues/1467
https://github.com/LibreHardwareMonitor/LibreHardwareMonitor/issues/1418

* Update Amd17Cpu.cs

* Update Amd17Cpu.cs

---------

Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2024-09-20 10:21:21 +02:00
PhyxionNL c0f2740ed3 Move mutexes out of Ring0 2023-06-14 11:58:26 +02:00
PhyxionNL cd77cec0b5 Unify CPU namespace with folder (#1023) 2023-03-21 18:11:40 +01:00
sebastian-devandPhyxionNL fe326e8877 Zen 4 SMU Update (#915) 
* Zen 4 SMU Update

* Misc

Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
 2022-12-01 10:52:10 +01:00
PhyxionNL 58cef111a1 Use file-scoped namespaces (#842) 2022-10-09 13:22:57 +02:00
PhyxionNL 3ac329f247 Fix some code analysis issues (#841) 2022-10-09 13:16:31 +02:00
PhyxionNL 38b97e10d0 Update editorconfig + changes (#771) 2022-06-29 19:38:57 +02:00
kolos 3df898af24 Add Ryzen SMU support (#428) 
Thanks to @kolos.
 2021-06-11 09:36:17 +02:00
kolos d14557fdea Enable reporting SoC voltage for Zen+ APUs (#424) 2021-04-11 13:55:58 +02:00
PhyxionNL 4b12fed029 Update Amd17Cpu.cs 
Clean up comments a bit.
 2021-02-08 10:51:40 +01:00
sebastian-dev 46150305f2 AMD Ryzen, wrong CPU Core Enumeration (#376) 
Thanks to @sebastian-dev
 2021-02-08 10:50:06 +01:00
PhyxionNL ea484f5c55 Use bus speed on AMD's Ryzen CPUs 
Fixes #329.
 2020-11-20 10:07:58 +01:00
Lucas Towers a80b455eaa Add support for AMD Ryzen 5000 processors (#328) 
* Add bare-minimum support for family 0x19

* Treat Zen 3 like Zen 2 in most-cases

* Remove mistakenly added whitespace
 2020-11-14 20:16:51 +01:00
sebastian-dev 22858791e9 Bugfix: AMD 39xx CCD Temperatures (#289) 2020-08-11 09:22:28 +02:00
sebastian-dev 0eaedcbbd6 AMD17, Bus Clock and Core 1 has the same Hardware id (#264) 2020-05-29 11:34:52 +02:00
sebastian-dev 7dd2af97bf Add Mutex release in Amd17. 
Thanks to @sebastian-dev
 2020-05-27 11:16:27 +02:00
Phyxion b118b7a2f1 Add support for Global\\Access_PCI mutex 
Based on the work of @moellerm
 2020-05-25 12:04:28 +02:00
Phyxion 3cc3d9139c Add support for multiple processor groups. 
Merge from upstream.
 2020-05-11 13:29:52 +02:00
Phyxion ec01af6cd0 Update Amd17Cpu.cs 
Fixes #237
 2020-05-03 22:29:01 +02:00
Phyxion 5bd108167d Restore OHM in copyright statement 2020-02-28 11:39:25 +01:00
Phyxion 2c44ddd7f4 Partially addresses #200 2020-01-28 16:43:43 +01:00
PhyxionandRaINi_ f7278652b5 Add Zen 2 CCD temperatures and merged Tdie/Tctl. 
Based on the work of @LeagueRaINi

Co-Authored-By: RaINi_ <razor13372k@gmail.com>
 2020-01-17 12:10:15 +01:00
Phyxion d26dcc4189 Update Ryzen temperature offsets 
Fixes #176
 2019-12-13 14:58:03 +01:00
RaINi_ 95fdd4920d Add SoC voltage for Ryzen 2 
Thanks to @LeagueRaINi
 2019-12-13 14:40:56 +01:00
Phyxion 73378f7c7b Code style #130 (#132) 
This closes #99.
 2019-09-23 19:29:10 +02:00