* Nct677X fix mutex acess with other devices an multiple instances
Fix the access with multiple devices.
Issue: #1243
Improper accessing the Nuvoton eSIO causes problems with other monitoring software
* Fix timeout behavior,
ensure the wait loop abort after a defined time
* Update timeout behavior and Code Formatting
* Update timeout behavior
* Add EC support for Z490 ROG MAXIMUS XII HERO (WI-FI)
* Update EmbeddedController.cs
Removed the broken line
* Update EmbeddedController.cs
Added the line back
* Update EmbeddedController.cs
Removed comment
* Update EmbeddedController.cs
Sorted by sensor address
* Check before entering bugged 0x4E IT87
* Specify fan control registers for IT8792E
* Refactor chip ID reading using TryReadWord
* Introduce ECIO gigabyte EC control
* Add ECIO compatibility check
* Refactor to consider result of read/write
* Refactor styles and syntaxes
* Rename SMFI to Smfi
* Remove public modifier for consistency
* Update code style
* Increase timeout and remove sleep for ecio waits
* Remove extra WaitIBE
* Rename IT8795E to IT87952E
IT8795E and IT87952E are distinct chips (with their own IC markings).
The IT8795E, as the IT8791E and IT8792E, reports chip ID 0x8733 whereas
the IT87952E identifies as 0x8695.
* Gigabyte EC: Fix typo in LPC register restore
When the AMD LPC Bridge registers are restored after configuring memory
mapping, restore the correct value for the "Memory Address for LPC
target cycles" register.
* Add IT87952E fan control for Gigabyte boards
IT87952E (ID 0x8695) has a third byte in SuperIO config space
(LDN 0x0F) that determines more bits of the host address for LPC memory
mapping.
Also the base address for Gigabyte boards is 0xFC000000 instead of
0xFF000000 (as is the case with IT8790/1/2/5).
This should make additional fan controls work on Gigabyte mainboards
where the settings had no effect previously, e.g: X570S AORUS MASTER
and X670E AORUS MASTER. (cf. Issue #251)
It does not yet work for Intel boards as the LPC bridge requires
different programming.
* Update LpcIO.cs
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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
* Adding checks around the value cache in the IPMI update to prevent null dereference.
* Adding braces for code style.
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Co-authored-by: doolbneerg <doolbneerg@outlook.com>
Correction of the motherboard model (CROSSHAIR III FORMULA > ROG CROSSHAIR VIII FORMULA). It has the same sensors so I put it with the CROSSHAIR VIII HERO
* EC: add CPU core voltage sensor
* Introfuce BoardInfo struct for storing EC initialization data
We need to keep some more information about the current board than just
the sensors set and this allows us do not duplicate sensor definitions for
such board variants as " (WI-FI)" when sensors are identical to the base variant.
* EC: add board families
* fixup! EC: add board families
* EC: add Amd 400 series
- Adds support for SYS_FAN4_PUMP control and tachometer
- Adds support for PCH temperature sensor
- There is a DDR5 version of this board out there, I don't know if it differs besides RAM.
sebastian-dev