* Add Gigabyte B550 AORUS Elite (v1/v2) models
* Add B550 Gaming X (v1 and v2) models as their layout is identical too
* Add B550 AORUS Pro v2
* Add B550M AORUS Elite
* Add the rest of Gigabyte B550 and B550M (Except the Vision D, Aorus Master, B550M Aorus Pro models)
* Add B550 UD AC Y1
System integrators such as iBuyPower and CyberPowerPC have sold systems with this OEM branded model, and thus would not be detected within this PR otherwise.
* Add B550M Pro, B550 Aorus Master, B550 Vision D models
* Add B550I AORUS PRO AX
* Rename EC_TEMP# to a more display friendly name
* Nct677X fix mutex acess with other devices an multiple instances
Fix the access with multiple devices.
Issue: #1243
Improper accessing the Nuvoton eSIO causes problems with other monitoring software
* Fix timeout behavior,
ensure the wait loop abort after a defined time
* Update timeout behavior and Code Formatting
* Update timeout behavior
* Add EC support for Z490 ROG MAXIMUS XII HERO (WI-FI)
* Update EmbeddedController.cs
Removed the broken line
* Update EmbeddedController.cs
Added the line back
* Update EmbeddedController.cs
Removed comment
* Update EmbeddedController.cs
Sorted by sensor address
* Add B450M DS3H and its variants
Note: From what I've seen some DS3H will report with a -CF suffix. Unsure if this applies to all B450 models or just a select few. Will be researching more
* Add the rest of B450M
* Add all Gigabyte B450 models
* Remove AVCC3
This is not a real source, especially since we already have the +3.3V rail
* Initial implementation of ASRock Z690 Extreme (voltages to be implemented later)
* Add voltages
* Update pull requests.yml
* This branch is not supposed to have this
* Add remaining voltages
* Fix incorrect voltage calculations and namings
* Use suggested names
VCCIN -> CPU Input Voltage
Unidentified names will use the generic names, and will be hidden by default.
* Add the other ASRock motherboards that are identical to the Z690 Extreme
* This was an accident
* Use more descriptive names
* Fix doubled Vcore value
* Remove bogus voltage sensors
* Separate Z690 Steel Legend
* Update SuperIOHardware.cs
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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
* Add ASUS TUF X570-WiFi (as a test)
* Add proper fan controls + attempt at proper temp detection
* Update pull requests.yml
* Remove non detected/wrong values
* Remove the need of GitHub actions on my fork
* B150M-C D3
* Update Identification.cs
* B150M-C
I'm not sure about the sensors, I took the z170 as a basis.
* B150M-C
Sorry for the redundancy.
* Fix Model
* Fix SuperIOHardware.cs
* Fix Identification.cs
* Correction
* Correction
* Check before entering bugged 0x4E IT87
* Specify fan control registers for IT8792E
* Refactor chip ID reading using TryReadWord
* Introduce ECIO gigabyte EC control
* Add ECIO compatibility check
* Refactor to consider result of read/write
* Refactor styles and syntaxes
* Rename SMFI to Smfi
* Remove public modifier for consistency
* Update code style
* Increase timeout and remove sleep for ecio waits
* Remove extra WaitIBE
* Add index to superIO identifier if required
* Simplify the index logic to 1 dictionary
* Unwanted B660M config delete.
* Simplify SuperIOHardware indexing
* Rename IT8795E to IT87952E
IT8795E and IT87952E are distinct chips (with their own IC markings).
The IT8795E, as the IT8791E and IT8792E, reports chip ID 0x8733 whereas
the IT87952E identifies as 0x8695.
* Gigabyte EC: Fix typo in LPC register restore
When the AMD LPC Bridge registers are restored after configuring memory
mapping, restore the correct value for the "Memory Address for LPC
target cycles" register.
* Add IT87952E fan control for Gigabyte boards
IT87952E (ID 0x8695) has a third byte in SuperIO config space
(LDN 0x0F) that determines more bits of the host address for LPC memory
mapping.
Also the base address for Gigabyte boards is 0xFC000000 instead of
0xFF000000 (as is the case with IT8790/1/2/5).
This should make additional fan controls work on Gigabyte mainboards
where the settings had no effect previously, e.g: X570S AORUS MASTER
and X670E AORUS MASTER. (cf. Issue #251)
It does not yet work for Intel boards as the LPC bridge requires
different programming.
* Update LpcIO.cs
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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
* Adding checks around the value cache in the IPMI update to prevent null dereference.
* Adding braces for code style.
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Co-authored-by: doolbneerg <doolbneerg@outlook.com>
Tellinq