sebastian-dev and PhyxionNL
342c4f5f52
Ryzen 9000 Core Frequency Bugfix ( #1548 )
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* Ryzen 9000 Core Frequency Bugfix
Zen5 (Ryzen 9000) has a changed register mapping for readout core frequency
* Update Ryzen 9000 and Core Clock
* fixed Package Power and Core power Calculation, use ESU for power scaling
* Changed DateTime.Now to UtcNow (better performance)
* Added Effective core clock
* Added Average Core clock and Average effective clock
* Remove Effective clock from SMU
Core effective clock is now calculated in Amd17Cpu/Core
* Fix Clock Ratio calculation.
Ratio > 1 is not possible
* Update Amd17Cpu.cs
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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com >
2025-02-04 16:43:51 +01:00
PhyxionNL
c0f2740ed3
Move mutexes out of Ring0
2023-06-14 11:58:26 +02:00
PhyxionNL
77f2e4b399
Don't request all access for OpenSCManager
2023-03-23 10:46:55 +01:00
PhyxionNL
fd723f38ed
Ring0 and InpOut cleanup ( #898 )
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Also GZip resources for crappy AV and update editorconfig for static fields.
2022-11-18 18:56:10 +01:00
PhyxionNL
58cef111a1
Use file-scoped namespaces ( #842 )
2022-10-09 13:22:57 +02:00
PhyxionNL
3ac329f247
Fix some code analysis issues ( #841 )
2022-10-09 13:16:31 +02:00
Ken Svensson
3bc334205f
Cleaned up mutex security code. ( #758 )
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Thanks to @Svek.
2022-06-24 09:34:24 +02:00
Argotronic UG and Udo
b38699508a
Fix usage of wrong mutex for access to Embedded Controllers ( #693 )
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* Extend Ring0.cs for EC Mutex (#691 )
* Acquire correct mutex when accessing ECs (#691 )
Co-authored-by: Udo <noreply@argotronic.com >
2022-03-15 11:27:53 +01:00
PhyxionNL
588a62862a
Also try using executing assembly name as service name for Ring0
2022-01-13 10:17:41 +01:00
PhyxionNL
a10c33ec0a
WinRing0 revert ( #478 )
2021-06-21 18:30:21 +02:00
kolos
3df898af24
Add Ryzen SMU support ( #428 )
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Thanks to @kolos.
2021-06-11 09:36:17 +02:00
Pomian
9ee5238798
NET5 support ( #312 )
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Thanks to @Pomianowski
2020-11-24 10:01:15 +01:00
PhyxionNL
8210cc2516
Switch to new csproj format. ( #308 )
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* Switch to new csproj
2020-10-02 15:05:52 +02:00
Phyxion
b118b7a2f1
Add support for Global\\Access_PCI mutex
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Based on the work of @moellerm
2020-05-25 12:04:28 +02:00
Phyxion
3cc3d9139c
Add support for multiple processor groups.
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Merge from upstream.
2020-05-11 13:29:52 +02:00
Phyxion
5bd108167d
Restore OHM in copyright statement
2020-02-28 11:39:25 +01:00
Phyxion
73378f7c7b
Code style #130 ( #132 )
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This closes #99 .
2019-09-23 19:29:10 +02:00
