ADL finds multiple logical gpus, this commit avoids multiple
unneeded initializations of AmdGpu class. The main control is moved to
AmdGpuGroup and the ADL_* calls are updated to ADL2_*, using the
context. Adapters using PMlog should be initialized only if sensors are
detected, adapters that pmlog is not enabled or doesn't work, should
fallback previous logic.
* Refactor ADL sensors update
- Check support for each sensor, on OD8 and new PMLog.
- Exclude cards before Vega10 from using PMLog
- Better validation for individual sensor support (for now asic-power/board-power)
- Validate pmlog struct using the lastUpdate, there are situations the
sensors values are corrupted, maybe because something blocking the pointer access to
the struct, but this needs to be verified.
* Update AmdGpu.cs
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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
According to the specification v.3.3.0, Chapter 7.18, Table 74,
the Size row:
> If the size is 32 GB-1 MB or greater, the
> field value is 7FFFh and the actual size is stored in
> the Extended Size field.
Therefore the Extended Size should replace the value of Size if
the latter equals 0x7FFF. The Extended Size should not be added
to Size.
Also, since Extended Size is DWORD, Size should not be ushort.
* Add ADL pmlog support, fix metrics on newer gpus
Newer GPUs needs this to show performance metrics properly. Sample rate
is hard coded (1000ms).
* Clean up
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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
* Add index to superIO identifier if required
* Simplify the index logic to 1 dictionary
* Unwanted B660M config delete.
* Simplify SuperIOHardware indexing
* Rename IT8795E to IT87952E
IT8795E and IT87952E are distinct chips (with their own IC markings).
The IT8795E, as the IT8791E and IT8792E, reports chip ID 0x8733 whereas
the IT87952E identifies as 0x8695.
* Gigabyte EC: Fix typo in LPC register restore
When the AMD LPC Bridge registers are restored after configuring memory
mapping, restore the correct value for the "Memory Address for LPC
target cycles" register.
* Add IT87952E fan control for Gigabyte boards
IT87952E (ID 0x8695) has a third byte in SuperIO config space
(LDN 0x0F) that determines more bits of the host address for LPC memory
mapping.
Also the base address for Gigabyte boards is 0xFC000000 instead of
0xFF000000 (as is the case with IT8790/1/2/5).
This should make additional fan controls work on Gigabyte mainboards
where the settings had no effect previously, e.g: X570S AORUS MASTER
and X670E AORUS MASTER. (cf. Issue #251)
It does not yet work for Intel boards as the LPC bridge requires
different programming.
* Update LpcIO.cs
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Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
new Krakens 2023 have a slightly different header
when setting fan speed:
- when setting fan speed byte 3 and 4 must be `0x1 0x1` instead of `0x0 0x0`
- when setting pump speed byte 3 and 4 must be `0x1 0x0` instead of `0x0
0x0` (but even `0x0 0x0`) works for some reason
Emerson Pinter