* Add support for Intel Panther Lake microarchitecture
* Reorder RaptorLake in CPU microarchitecture list
* Handle unknown microarchitecture case in IntelCpu
* Refactor Intel CPU microarchitecture detection
* NVIDIA GPU: reserve load index 3 for GPU Memory, remap other loads
* NVIDIA GPU: simplify load sensor indexing
* NVIDIA GPU: create GPU Memory load after utilization loads
Place the GPU Memory Load sensor before power topology and D3D node loads
so it appears with other GPU metrics in the UI. Load indices advance in
the same order as before for uniqueness.
* NVIDIA GPU: use local nextLoadIndex in constructor
Replace the instance field with a ctor-local counter for Load sensor indices.
* feat: Add Native AOT compilation support for LibreHardwareMonitorLib
- Replace non-generic Marshal.GetDelegateForFunctionPointer with generic versions
(NvApi.cs, NvidiaML.cs, OpCode.cs)
- Replace non-generic Marshal.PtrToStructure/SizeOf with generic versions
(AtiAdlxx.cs, AmdGpu.cs, Ipmi.cs)
- Replace reflection-based Mono.Posix calls with direct Syscall for non-NETFRAMEWORK
(OpCode.cs)
- Add DynamicallyAccessedMembers annotations for trim-safe generic marshaling
(MsiCoreLiquidController.cs, WireViewPro2.cs)
- Add IsAotCompatible, IsTrimmable, and AOT/trim analyzers to csproj for net8.0+
- All changes maintain full backward compatibility with net472/netstandard2.0
Tested: dotnet publish with PublishAot=true on net10.0 win-x64 succeeds.
AOT binary correctly enumerates all hardware and sensors without errors.
* feat: Add conditional compilation for .NET 5.0 or greater in various classes
* feat: Add AOT test project and update workflows for AOT compilation
* Drop test project
* NET5_0_OR_GREATER > NET
---------
Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
* Add NCT6687DR fan control support with bit mapping and configuration phase handling
* NCT6687DR: emulate CC_Engine SetManualFAN protocol
- System fans (index > 8): skip manual mode bit (0xA00), use flat SmartFAN curve instead
- Change commit value from 0x40 to 0xC0 (REQ|DONE) matching CC_Engine
- Write 7-point temp curve (all 0x20/32C) alongside duty curve for system fans
- Add Sleep(10ms) after request (0x80) and commit (0xC0) per CC_Engine timing
- Restore: only clear manual mode bit for CPU/Pump/Chipset/EZ-Connect fans
* NCT6687DR: add INVALID bit check with retry after EC commit
- FinishFanCfgUpdate now returns bool: false if EC sets INVALID (0xCF8 & 0x10)
- SetControl and RestoreDefaultFanControl retry up to 3 times on INVALID
- Matches CC_Engine's post-commit validation behavior
* fix(NCT6687DR): bypass SmartFAN engine for system fans — use direct PWM
System fans (SYSFAN1-7) now use the same direct PWM mechanism as
CPU/Pump/Chipset fans, completely bypassing the SmartFAN curve engine
and its inherent ~2%/sec PWM smoothing.
Key changes:
- FAN_PWM_COMMAND_REG: system fans now point to direct PWM registers
(SYSFAN7: 08:E9, SYSFAN1-6: 02:65..02:60) instead of SmartFAN
curve base addresses (0xBE0..0xC70)
- FAN_CONTROL_MODE_REG: system fans use 08:0F (not 0xA00) for their
manual-mode enable bits
- FAN_CONTROL_MODE_BIT: corrected per-channel bit positions derived
from BIOS unk_104C0 table (sub_2F50 / sub_2BDC analysis)
- Set6687DRControl: simplified to single WriteByte for all fans
(no more 7-point flat curve + step/rate writes)
- SetControl: unified path — all fans set manual-mode bit + direct PWM
- RestoreDefaultFanControl: clear manual-mode bit to return to SmartFAN
Register mapping discovered via IDA analysis of BIOS firmware:
- Extended unk_101E0 table at 0x103AC contains channels 10-15
- sub_2BDC configures 5 register operations per channel before curve write
- Entry[1] in unk_104C0 = manual-mode enable register + bit position
* review: Stopwatch, engineSts rename, CompleteFanConfigUpdate
* refactor: PreciseWait via SpinWait, DateTime to Stopwatch in ReadByte/WriteByte
* review: remove regions, revert PreciseWait to Thread.Sleep
JMR-dev
