919 lines
21 KiB
C
919 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <sys/ptrace.h>
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#include <sys/types.h>
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#include <sys/wait.h>
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#include <sys/uio.h>
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#include <unistd.h>
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#include <errno.h>
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#include <linux/ptrace.h>
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#include <linux/elf.h>
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#include "kselftest_harness.h"
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#include "v_helpers.h"
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#define SR_FS_DIRTY 0x00006000UL
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#define CSR_VXRM_SHIFT 1
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volatile unsigned long chld_lock;
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TEST(ptrace_v_not_enabled)
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{
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pid_t pid;
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if (!(is_vector_supported() || is_xtheadvector_supported()))
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SKIP(return, "Vector not supported");
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chld_lock = 1;
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pid = fork();
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ASSERT_LE(0, pid)
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TH_LOG("fork: %m");
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if (pid == 0) {
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while (chld_lock == 1)
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asm volatile("" : : "g"(chld_lock) : "memory");
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asm volatile ("ebreak" : : : );
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} else {
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struct __riscv_v_regset_state *regset_data;
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unsigned long vlenb = get_vr_len();
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size_t regset_size;
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struct iovec iov;
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int status;
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int ret;
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/* attach */
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ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL));
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ASSERT_EQ(pid, waitpid(pid, &status, 0));
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ASSERT_TRUE(WIFSTOPPED(status));
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/* unlock */
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ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0));
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/* resume and wait for ebreak */
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ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
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ASSERT_EQ(pid, waitpid(pid, &status, 0));
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ASSERT_TRUE(WIFSTOPPED(status));
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/* try to read vector registers from the tracee */
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regset_size = sizeof(*regset_data) + vlenb * 32;
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regset_data = calloc(1, regset_size);
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iov.iov_base = regset_data;
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iov.iov_len = regset_size;
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/* V extension is available, but not yet enabled for the tracee */
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errno = 0;
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ret = ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov);
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ASSERT_EQ(ENODATA, errno);
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ASSERT_EQ(-1, ret);
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/* cleanup */
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ASSERT_EQ(0, kill(pid, SIGKILL));
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}
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}
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TEST(ptrace_v_early_debug)
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{
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static volatile unsigned long vstart;
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static volatile unsigned long vtype;
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static volatile unsigned long vlenb;
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static volatile unsigned long vcsr;
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static volatile unsigned long vl;
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bool xtheadvector;
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pid_t pid;
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if (!(is_vector_supported() || is_xtheadvector_supported()))
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SKIP(return, "Vector not supported");
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xtheadvector = is_xtheadvector_supported();
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chld_lock = 1;
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pid = fork();
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ASSERT_LE(0, pid)
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TH_LOG("fork: %m");
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if (pid == 0) {
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unsigned long vxsat, vxrm;
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vlenb = get_vr_len();
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while (chld_lock == 1)
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asm volatile ("" : : "g"(chld_lock) : "memory");
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asm volatile (
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"csrr %[vstart], vstart\n"
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"csrr %[vtype], vtype\n"
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"csrr %[vl], vl\n"
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: [vtype] "=r"(vtype), [vstart] "=r"(vstart), [vl] "=r"(vl)
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:
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: "memory");
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/* no 'is_xtheadvector_supported()' here to avoid clobbering v-state by syscall */
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if (xtheadvector) {
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asm volatile (
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"csrs sstatus, %[bit]\n"
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"csrr %[vxsat], vxsat\n"
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"csrr %[vxrm], vxrm\n"
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: [vxsat] "=r"(vxsat), [vxrm] "=r"(vxrm)
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: [bit] "r" (SR_FS_DIRTY)
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: "memory");
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vcsr = vxsat | vxrm << CSR_VXRM_SHIFT;
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} else {
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asm volatile (
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"csrr %[vcsr], vcsr\n"
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: [vcsr] "=r"(vcsr)
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:
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: "memory");
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}
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asm volatile (
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".option push\n"
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".option norvc\n"
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"ebreak\n"
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".option pop\n");
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} else {
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struct __riscv_v_regset_state *regset_data;
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unsigned long vstart_csr;
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unsigned long vlenb_csr;
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unsigned long vtype_csr;
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unsigned long vcsr_csr;
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unsigned long vl_csr;
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size_t regset_size;
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struct iovec iov;
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int status;
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/* attach */
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ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL));
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ASSERT_EQ(pid, waitpid(pid, &status, 0));
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ASSERT_TRUE(WIFSTOPPED(status));
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/* unlock */
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ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0));
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/* resume and wait for ebreak */
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ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
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ASSERT_EQ(pid, waitpid(pid, &status, 0));
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ASSERT_TRUE(WIFSTOPPED(status));
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/* read tracee vector csr regs using ptrace PEEKDATA */
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errno = 0;
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vstart_csr = ptrace(PTRACE_PEEKDATA, pid, &vstart, NULL);
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ASSERT_FALSE((errno != 0) && (vstart_csr == -1));
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errno = 0;
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vl_csr = ptrace(PTRACE_PEEKDATA, pid, &vl, NULL);
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ASSERT_FALSE((errno != 0) && (vl_csr == -1));
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errno = 0;
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vtype_csr = ptrace(PTRACE_PEEKDATA, pid, &vtype, NULL);
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ASSERT_FALSE((errno != 0) && (vtype_csr == -1));
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errno = 0;
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vcsr_csr = ptrace(PTRACE_PEEKDATA, pid, &vcsr, NULL);
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ASSERT_FALSE((errno != 0) && (vcsr_csr == -1));
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errno = 0;
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vlenb_csr = ptrace(PTRACE_PEEKDATA, pid, &vlenb, NULL);
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ASSERT_FALSE((errno != 0) && (vlenb_csr == -1));
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/* read tracee csr regs using ptrace GETREGSET */
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regset_size = sizeof(*regset_data) + vlenb_csr * 32;
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regset_data = calloc(1, regset_size);
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iov.iov_base = regset_data;
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iov.iov_len = regset_size;
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ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov));
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/* compare */
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EXPECT_EQ(vstart_csr, regset_data->vstart);
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EXPECT_EQ(vtype_csr, regset_data->vtype);
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EXPECT_EQ(vlenb_csr, regset_data->vlenb);
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EXPECT_EQ(vcsr_csr, regset_data->vcsr);
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EXPECT_EQ(vl_csr, regset_data->vl);
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/* cleanup */
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ASSERT_EQ(0, kill(pid, SIGKILL));
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}
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}
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TEST(ptrace_v_syscall_clobbering)
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{
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pid_t pid;
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if (!is_vector_supported() && !is_xtheadvector_supported())
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SKIP(return, "Vector not supported");
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chld_lock = 1;
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pid = fork();
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ASSERT_LE(0, pid)
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TH_LOG("fork: %m");
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if (pid == 0) {
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unsigned long vl;
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while (chld_lock == 1)
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asm volatile("" : : "g"(chld_lock) : "memory");
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if (is_xtheadvector_supported()) {
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asm volatile (
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// 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli
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// vsetvli t4, x0, e16, m2, d1
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".4byte 0b00000000010100000111111011010111\n"
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"mv %[new_vl], t4\n"
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: [new_vl] "=r" (vl) : : "t4");
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} else {
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asm volatile (
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".option push\n"
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".option arch, +zve32x\n"
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"vsetvli %[new_vl], x0, e16, m2, tu, mu\n"
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".option pop\n"
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: [new_vl] "=r"(vl) : : );
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}
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while (1) {
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asm volatile (
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".option push\n"
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".option norvc\n"
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"ebreak\n"
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".option pop\n");
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sleep(0);
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}
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} else {
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struct __riscv_v_regset_state *regset_data;
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unsigned long vlenb = get_vr_len();
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struct user_regs_struct regs;
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size_t regset_size;
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struct iovec iov;
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int status;
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/* attach */
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ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL));
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ASSERT_EQ(pid, waitpid(pid, &status, 0));
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ASSERT_TRUE(WIFSTOPPED(status));
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/* unlock */
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ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0));
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/* resume and wait for the 1st ebreak */
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ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
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ASSERT_EQ(pid, waitpid(pid, &status, 0));
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ASSERT_TRUE(WIFSTOPPED(status));
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/* read tracee vector csr regs using ptrace GETREGSET */
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regset_size = sizeof(*regset_data) + vlenb * 32;
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regset_data = calloc(1, regset_size);
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iov.iov_base = regset_data;
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iov.iov_len = regset_size;
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ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov));
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/* verify initial vsetvli settings */
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if (is_xtheadvector_supported()) {
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EXPECT_EQ(5UL, regset_data->vtype);
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} else {
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EXPECT_EQ(9UL, regset_data->vtype);
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}
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EXPECT_EQ(regset_data->vlenb, regset_data->vl);
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EXPECT_EQ(vlenb, regset_data->vlenb);
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EXPECT_EQ(0UL, regset_data->vstart);
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EXPECT_EQ(0UL, regset_data->vcsr);
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/* skip 1st ebreak, then resume and wait for the 2nd ebreak */
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iov.iov_base = ®s;
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iov.iov_len = sizeof(regs);
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ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_PRSTATUS, &iov));
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regs.pc += 4;
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ASSERT_EQ(0, ptrace(PTRACE_SETREGSET, pid, NT_PRSTATUS, &iov));
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ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
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ASSERT_EQ(pid, waitpid(pid, &status, 0));
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ASSERT_TRUE(WIFSTOPPED(status));
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/* read tracee vtype using ptrace GETREGSET */
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iov.iov_base = regset_data;
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iov.iov_len = regset_size;
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ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov));
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/* verify that V state is illegal after syscall */
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EXPECT_EQ((1UL << (__riscv_xlen - 1)), regset_data->vtype);
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EXPECT_EQ(vlenb, regset_data->vlenb);
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EXPECT_EQ(0UL, regset_data->vstart);
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EXPECT_EQ(0UL, regset_data->vcsr);
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EXPECT_EQ(0UL, regset_data->vl);
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/* cleanup */
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ASSERT_EQ(0, kill(pid, SIGKILL));
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}
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}
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FIXTURE(v_csr_invalid)
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{
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};
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FIXTURE_SETUP(v_csr_invalid)
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{
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}
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FIXTURE_TEARDOWN(v_csr_invalid)
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{
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}
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#define VECTOR_1_0 _BITUL(0)
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#define XTHEAD_VECTOR_0_7 _BITUL(1)
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#define vector_test(x) ((x) & VECTOR_1_0)
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#define xthead_test(x) ((x) & XTHEAD_VECTOR_0_7)
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/* modifications of the initial vsetvli settings */
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FIXTURE_VARIANT(v_csr_invalid)
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{
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unsigned long vstart;
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unsigned long vl;
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unsigned long vtype;
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unsigned long vcsr;
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unsigned long vlenb_mul;
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unsigned long vlenb_min;
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unsigned long vlenb_max;
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unsigned long spec;
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};
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/* unexpected vlenb value */
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FIXTURE_VARIANT_ADD(v_csr_invalid, new_vlenb)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x3,
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.vcsr = 0x0,
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.vlenb_mul = 0x2,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,
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};
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/* invalid reserved bits in vcsr */
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FIXTURE_VARIANT_ADD(v_csr_invalid, vcsr_invalid_reserved_bits)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x3,
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.vcsr = 0x1UL << 8,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,
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};
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/* invalid reserved bits in vtype */
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FIXTURE_VARIANT_ADD(v_csr_invalid, vtype_invalid_reserved_bits)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = (0x1UL << 8) | 0x3,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,
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};
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/* set vill bit */
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FIXTURE_VARIANT_ADD(v_csr_invalid, invalid_vill_bit)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = (0x1UL << (__riscv_xlen - 1)) | 0x3,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,
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};
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/* reserved vsew value: vsew > 3 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vsew)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x4UL << 3,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0,
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};
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/* XTheadVector: unsupported non-zero VEDIV value */
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FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vediv)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x3UL << 5,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = XTHEAD_VECTOR_0_7,
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};
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/* reserved vlmul value: vlmul == 4 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vlmul)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x4,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0,
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};
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/* invalid fractional LMUL for VLEN <= 256: LMUL= 1/8, SEW = 64 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, frac_lmul1)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x1d,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x20,
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.spec = VECTOR_1_0,
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};
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/* invalid integral LMUL for VLEN <= 16: LMUL= 2, SEW = 64 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, int_lmul1)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x19,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x2,
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.spec = VECTOR_1_0,
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};
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/* XTheadVector: invalid integral LMUL for VLEN <= 16: LMUL= 2, SEW = 64 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, int_lmul2)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0xd,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x2,
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.spec = XTHEAD_VECTOR_0_7,
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};
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/* invalid VL for VLEN <= 128: LMUL= 2, SEW = 64, VL = 8 */
|
|
FIXTURE_VARIANT_ADD(v_csr_invalid, vl1)
|
|
{
|
|
.vstart = 0x0,
|
|
.vl = 0x8,
|
|
.vtype = 0x19,
|
|
.vcsr = 0x0,
|
|
.vlenb_mul = 0x1,
|
|
.vlenb_min = 0x0,
|
|
.vlenb_max = 0x10,
|
|
.spec = VECTOR_1_0,
|
|
};
|
|
|
|
/* XTheadVector: invalid VL for VLEN <= 128: LMUL= 2, SEW = 64, VL = 8 */
|
|
FIXTURE_VARIANT_ADD(v_csr_invalid, vl2)
|
|
{
|
|
.vstart = 0x0,
|
|
.vl = 0x8,
|
|
.vtype = 0xd,
|
|
.vcsr = 0x0,
|
|
.vlenb_mul = 0x1,
|
|
.vlenb_min = 0x0,
|
|
.vlenb_max = 0x10,
|
|
.spec = XTHEAD_VECTOR_0_7,
|
|
};
|
|
|
|
TEST_F(v_csr_invalid, ptrace_v_invalid_values)
|
|
{
|
|
unsigned long vlenb;
|
|
pid_t pid;
|
|
|
|
if (!is_vector_supported() && !is_xtheadvector_supported())
|
|
SKIP(return, "Vectors not supported");
|
|
|
|
if (is_vector_supported() && !vector_test(variant->spec))
|
|
SKIP(return, "Test not supported for Vector");
|
|
|
|
if (is_xtheadvector_supported() && !xthead_test(variant->spec))
|
|
SKIP(return, "Test not supported for XTheadVector");
|
|
|
|
vlenb = get_vr_len();
|
|
|
|
if (variant->vlenb_min) {
|
|
if (vlenb < variant->vlenb_min)
|
|
SKIP(return, "This test does not support VLEN < %lu\n",
|
|
variant->vlenb_min * 8);
|
|
}
|
|
|
|
if (variant->vlenb_max) {
|
|
if (vlenb > variant->vlenb_max)
|
|
SKIP(return, "This test does not support VLEN > %lu\n",
|
|
variant->vlenb_max * 8);
|
|
}
|
|
|
|
chld_lock = 1;
|
|
pid = fork();
|
|
ASSERT_LE(0, pid)
|
|
TH_LOG("fork: %m");
|
|
|
|
if (pid == 0) {
|
|
unsigned long vl;
|
|
|
|
while (chld_lock == 1)
|
|
asm volatile("" : : "g"(chld_lock) : "memory");
|
|
|
|
if (is_xtheadvector_supported()) {
|
|
asm volatile (
|
|
// 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli
|
|
// vsetvli t4, x0, e16, m2, d1
|
|
".4byte 0b00000000010100000111111011010111\n"
|
|
"mv %[new_vl], t4\n"
|
|
: [new_vl] "=r" (vl) : : "t4");
|
|
} else {
|
|
asm volatile (
|
|
".option push\n"
|
|
".option arch, +zve32x\n"
|
|
"vsetvli %[new_vl], x0, e16, m2, tu, mu\n"
|
|
".option pop\n"
|
|
: [new_vl] "=r"(vl) : : );
|
|
}
|
|
|
|
while (1) {
|
|
asm volatile (
|
|
".option push\n"
|
|
".option norvc\n"
|
|
"ebreak\n"
|
|
"nop\n"
|
|
".option pop\n");
|
|
}
|
|
} else {
|
|
struct __riscv_v_regset_state *regset_data;
|
|
size_t regset_size;
|
|
struct iovec iov;
|
|
int status;
|
|
int ret;
|
|
|
|
/* attach */
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL));
|
|
ASSERT_EQ(pid, waitpid(pid, &status, 0));
|
|
ASSERT_TRUE(WIFSTOPPED(status));
|
|
|
|
/* unlock */
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0));
|
|
|
|
/* resume and wait for the 1st ebreak */
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
|
|
ASSERT_EQ(pid, waitpid(pid, &status, 0));
|
|
ASSERT_TRUE(WIFSTOPPED(status));
|
|
|
|
/* read tracee vector csr regs using ptrace GETREGSET */
|
|
|
|
regset_size = sizeof(*regset_data) + vlenb * 32;
|
|
regset_data = calloc(1, regset_size);
|
|
|
|
iov.iov_base = regset_data;
|
|
iov.iov_len = regset_size;
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov));
|
|
|
|
/* verify initial vsetvli settings */
|
|
|
|
if (is_xtheadvector_supported()) {
|
|
EXPECT_EQ(5UL, regset_data->vtype);
|
|
} else {
|
|
EXPECT_EQ(9UL, regset_data->vtype);
|
|
}
|
|
|
|
EXPECT_EQ(regset_data->vlenb, regset_data->vl);
|
|
EXPECT_EQ(vlenb, regset_data->vlenb);
|
|
EXPECT_EQ(0UL, regset_data->vstart);
|
|
EXPECT_EQ(0UL, regset_data->vcsr);
|
|
|
|
/* apply invalid settings from fixture variants */
|
|
|
|
regset_data->vlenb *= variant->vlenb_mul;
|
|
regset_data->vstart = variant->vstart;
|
|
regset_data->vtype = variant->vtype;
|
|
regset_data->vcsr = variant->vcsr;
|
|
regset_data->vl = variant->vl;
|
|
|
|
iov.iov_base = regset_data;
|
|
iov.iov_len = regset_size;
|
|
|
|
errno = 0;
|
|
ret = ptrace(PTRACE_SETREGSET, pid, NT_RISCV_VECTOR, &iov);
|
|
ASSERT_EQ(errno, EINVAL);
|
|
ASSERT_EQ(ret, -1);
|
|
|
|
/* cleanup */
|
|
|
|
ASSERT_EQ(0, kill(pid, SIGKILL));
|
|
}
|
|
}
|
|
|
|
FIXTURE(v_csr_valid)
|
|
{
|
|
};
|
|
|
|
FIXTURE_SETUP(v_csr_valid)
|
|
{
|
|
}
|
|
|
|
FIXTURE_TEARDOWN(v_csr_valid)
|
|
{
|
|
}
|
|
|
|
/* modifications of the initial vsetvli settings */
|
|
FIXTURE_VARIANT(v_csr_valid)
|
|
{
|
|
unsigned long vstart;
|
|
unsigned long vl;
|
|
unsigned long vtype;
|
|
unsigned long vcsr;
|
|
unsigned long vlenb_mul;
|
|
unsigned long vlenb_min;
|
|
unsigned long vlenb_max;
|
|
unsigned long spec;
|
|
};
|
|
|
|
/* valid for VLEN >= 128: LMUL= 1/4, SEW = 32 */
|
|
FIXTURE_VARIANT_ADD(v_csr_valid, frac_lmul1)
|
|
{
|
|
.vstart = 0x0,
|
|
.vl = 0x0,
|
|
.vtype = 0x16,
|
|
.vcsr = 0x0,
|
|
.vlenb_mul = 0x1,
|
|
.vlenb_min = 0x10,
|
|
.vlenb_max = 0x0,
|
|
.spec = VECTOR_1_0,
|
|
};
|
|
|
|
/* valid for VLEN >= 16: LMUL= 2, SEW = 32 */
|
|
FIXTURE_VARIANT_ADD(v_csr_valid, int_lmul1)
|
|
{
|
|
.vstart = 0x0,
|
|
.vl = 0x0,
|
|
.vtype = 0x11,
|
|
.vcsr = 0x0,
|
|
.vlenb_mul = 0x1,
|
|
.vlenb_min = 0x2,
|
|
.vlenb_max = 0x0,
|
|
.spec = VECTOR_1_0,
|
|
};
|
|
|
|
/* valid for XTheadVector VLEN >= 16: LMUL= 2, SEW = 32 */
|
|
FIXTURE_VARIANT_ADD(v_csr_valid, int_lmul2)
|
|
{
|
|
.vstart = 0x0,
|
|
.vl = 0x0,
|
|
.vtype = 0x9,
|
|
.vcsr = 0x0,
|
|
.vlenb_mul = 0x1,
|
|
.vlenb_min = 0x2,
|
|
.vlenb_max = 0x0,
|
|
.spec = XTHEAD_VECTOR_0_7,
|
|
};
|
|
|
|
/* valid for VLEN >= 32: LMUL= 2, SEW = 32, VL = 2 */
|
|
FIXTURE_VARIANT_ADD(v_csr_valid, int_lmul3)
|
|
{
|
|
.vstart = 0x0,
|
|
.vl = 0x2,
|
|
.vtype = 0x11,
|
|
.vcsr = 0x0,
|
|
.vlenb_mul = 0x1,
|
|
.vlenb_min = 0x4,
|
|
.vlenb_max = 0x0,
|
|
.spec = VECTOR_1_0,
|
|
};
|
|
|
|
TEST_F(v_csr_valid, ptrace_v_valid_values)
|
|
{
|
|
unsigned long vlenb;
|
|
pid_t pid;
|
|
|
|
if (!is_vector_supported() && !is_xtheadvector_supported())
|
|
SKIP(return, "Vectors not supported");
|
|
|
|
if (is_vector_supported() && !vector_test(variant->spec))
|
|
SKIP(return, "Test not supported for Vector");
|
|
|
|
if (is_xtheadvector_supported() && !xthead_test(variant->spec))
|
|
SKIP(return, "Test not supported for XTheadVector");
|
|
|
|
vlenb = get_vr_len();
|
|
|
|
if (variant->vlenb_min) {
|
|
if (vlenb < variant->vlenb_min)
|
|
SKIP(return, "This test does not support VLEN < %lu\n",
|
|
variant->vlenb_min * 8);
|
|
}
|
|
if (variant->vlenb_max) {
|
|
if (vlenb > variant->vlenb_max)
|
|
SKIP(return, "This test does not support VLEN > %lu\n",
|
|
variant->vlenb_max * 8);
|
|
}
|
|
|
|
chld_lock = 1;
|
|
pid = fork();
|
|
ASSERT_LE(0, pid)
|
|
TH_LOG("fork: %m");
|
|
|
|
if (pid == 0) {
|
|
unsigned long vl;
|
|
|
|
while (chld_lock == 1)
|
|
asm volatile("" : : "g"(chld_lock) : "memory");
|
|
|
|
if (is_xtheadvector_supported()) {
|
|
asm volatile (
|
|
// 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli
|
|
// vsetvli t4, x0, e16, m2, d1
|
|
".4byte 0b00000000010100000111111011010111\n"
|
|
"mv %[new_vl], t4\n"
|
|
: [new_vl] "=r" (vl) : : "t4");
|
|
} else {
|
|
asm volatile (
|
|
".option push\n"
|
|
".option arch, +zve32x\n"
|
|
"vsetvli %[new_vl], x0, e16, m2, tu, mu\n"
|
|
".option pop\n"
|
|
: [new_vl] "=r"(vl) : : );
|
|
}
|
|
|
|
asm volatile (
|
|
".option push\n"
|
|
".option norvc\n"
|
|
".option arch, +zve32x\n"
|
|
"ebreak\n" /* breakpoint 1: apply new V state using ptrace */
|
|
"nop\n"
|
|
"ebreak\n" /* breakpoint 2: V state clean - context will not be saved */
|
|
"vmv.v.i v0, -1\n"
|
|
"ebreak\n" /* breakpoint 3: V state dirty - context will be saved */
|
|
".option pop\n");
|
|
} else {
|
|
struct __riscv_v_regset_state *regset_data;
|
|
struct user_regs_struct regs;
|
|
size_t regset_size;
|
|
struct iovec iov;
|
|
int status;
|
|
|
|
/* attach */
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL));
|
|
ASSERT_EQ(pid, waitpid(pid, &status, 0));
|
|
ASSERT_TRUE(WIFSTOPPED(status));
|
|
|
|
/* unlock */
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0));
|
|
|
|
/* resume and wait for the 1st ebreak */
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
|
|
ASSERT_EQ(pid, waitpid(pid, &status, 0));
|
|
ASSERT_TRUE(WIFSTOPPED(status));
|
|
|
|
/* read tracee vector csr regs using ptrace GETREGSET */
|
|
|
|
regset_size = sizeof(*regset_data) + vlenb * 32;
|
|
regset_data = calloc(1, regset_size);
|
|
|
|
iov.iov_base = regset_data;
|
|
iov.iov_len = regset_size;
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov));
|
|
|
|
/* verify initial vsetvli settings */
|
|
|
|
if (is_xtheadvector_supported()) {
|
|
EXPECT_EQ(5UL, regset_data->vtype);
|
|
} else {
|
|
EXPECT_EQ(9UL, regset_data->vtype);
|
|
}
|
|
|
|
EXPECT_EQ(regset_data->vlenb, regset_data->vl);
|
|
EXPECT_EQ(vlenb, regset_data->vlenb);
|
|
EXPECT_EQ(0UL, regset_data->vstart);
|
|
EXPECT_EQ(0UL, regset_data->vcsr);
|
|
|
|
/* apply valid settings from fixture variants */
|
|
|
|
regset_data->vlenb *= variant->vlenb_mul;
|
|
regset_data->vstart = variant->vstart;
|
|
regset_data->vtype = variant->vtype;
|
|
regset_data->vcsr = variant->vcsr;
|
|
regset_data->vl = variant->vl;
|
|
|
|
iov.iov_base = regset_data;
|
|
iov.iov_len = regset_size;
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_SETREGSET, pid, NT_RISCV_VECTOR, &iov));
|
|
|
|
/* skip 1st ebreak, then resume and wait for the 2nd ebreak */
|
|
|
|
iov.iov_base = ®s;
|
|
iov.iov_len = sizeof(regs);
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_PRSTATUS, &iov));
|
|
regs.pc += 4;
|
|
ASSERT_EQ(0, ptrace(PTRACE_SETREGSET, pid, NT_PRSTATUS, &iov));
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
|
|
ASSERT_EQ(pid, waitpid(pid, &status, 0));
|
|
ASSERT_TRUE(WIFSTOPPED(status));
|
|
|
|
/* read tracee vector csr regs using ptrace GETREGSET */
|
|
|
|
iov.iov_base = regset_data;
|
|
iov.iov_len = regset_size;
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov));
|
|
|
|
/* verify vector csr regs from tracee context */
|
|
|
|
EXPECT_EQ(regset_data->vstart, variant->vstart);
|
|
EXPECT_EQ(regset_data->vtype, variant->vtype);
|
|
EXPECT_EQ(regset_data->vcsr, variant->vcsr);
|
|
EXPECT_EQ(regset_data->vl, variant->vl);
|
|
EXPECT_EQ(regset_data->vlenb, vlenb);
|
|
|
|
/* skip 2nd ebreak, then resume and wait for the 3rd ebreak */
|
|
|
|
iov.iov_base = ®s;
|
|
iov.iov_len = sizeof(regs);
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_PRSTATUS, &iov));
|
|
regs.pc += 4;
|
|
ASSERT_EQ(0, ptrace(PTRACE_SETREGSET, pid, NT_PRSTATUS, &iov));
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
|
|
ASSERT_EQ(pid, waitpid(pid, &status, 0));
|
|
ASSERT_TRUE(WIFSTOPPED(status));
|
|
|
|
/* read tracee vector csr regs using ptrace GETREGSET */
|
|
|
|
iov.iov_base = regset_data;
|
|
iov.iov_len = regset_size;
|
|
|
|
ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov));
|
|
|
|
/* verify vector csr regs from tracee context */
|
|
|
|
EXPECT_EQ(regset_data->vstart, variant->vstart);
|
|
EXPECT_EQ(regset_data->vtype, variant->vtype);
|
|
EXPECT_EQ(regset_data->vcsr, variant->vcsr);
|
|
EXPECT_EQ(regset_data->vl, variant->vl);
|
|
EXPECT_EQ(regset_data->vlenb, vlenb);
|
|
|
|
/* cleanup */
|
|
|
|
ASSERT_EQ(0, kill(pid, SIGKILL));
|
|
}
|
|
}
|
|
|
|
TEST_HARNESS_MAIN
|