287 lines
8.6 KiB
C
287 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2025 Linaro Ltd
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*/
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#include <linux/iopoll.h>
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#include <linux/reset.h>
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#include "iris_instance.h"
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#include "iris_vpu_common.h"
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#include "iris_vpu_register_defines.h"
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#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18)
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#define SW_RESET BIT(0)
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#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
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#define NOC_HALT BIT(0)
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#define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28)
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static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core)
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{
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u32 value, pwr_status;
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value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS);
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pwr_status = value & BIT(1);
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return pwr_status ? false : true;
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}
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static void iris_vpu3_power_off_hardware(struct iris_core *core)
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{
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u32 reg_val = 0, value, i;
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int ret;
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if (iris_vpu3x_hw_power_collapsed(core))
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goto disable_power;
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dev_err(core->dev, "video hw is power on\n");
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value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
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if (value)
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writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
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for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {
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ret = readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 * i,
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reg_val, reg_val & 0x400000, 2000, 20000);
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if (ret)
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goto disable_power;
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}
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writel(VIDEO_NOC_RESET_REQ, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
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ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
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reg_val, reg_val & 0x3, 200, 2000);
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if (ret)
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goto disable_power;
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writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
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ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
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reg_val, !(reg_val & 0x3), 200, 2000);
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if (ret)
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goto disable_power;
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writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE,
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core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
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writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
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writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
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disable_power:
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iris_vpu_power_off_hw(core);
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}
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static void iris_vpu33_power_off_hardware(struct iris_core *core)
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{
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bool handshake_done = false, handshake_busy = false;
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u32 reg_val = 0, value, i;
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u32 count = 0;
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int ret;
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if (iris_vpu3x_hw_power_collapsed(core))
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goto disable_power;
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dev_err(core->dev, "video hw is power on\n");
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value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
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if (value)
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writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
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for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {
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ret = readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 * i,
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reg_val, reg_val & 0x400000, 2000, 20000);
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if (ret)
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goto disable_power;
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}
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/* Retry up to 1000 times as recommended by hardware documentation */
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do {
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/* set MNoC to low power */
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writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
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udelay(15);
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value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS);
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handshake_done = value & NOC_LPI_STATUS_DONE;
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handshake_busy = value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
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if (handshake_done || !handshake_busy)
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break;
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writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
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udelay(15);
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} while (++count < 1000);
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if (!handshake_done && handshake_busy)
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dev_err(core->dev, "LPI handshake timeout\n");
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ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
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reg_val, reg_val & BIT(0), 200, 2000);
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if (ret)
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goto disable_power;
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writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
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writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE,
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core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
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writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
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writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
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disable_power:
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iris_vpu_power_off_hw(core);
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}
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static int iris_vpu33_power_off_controller(struct iris_core *core)
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{
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u32 xo_rst_tbl_size = core->iris_platform_data->controller_rst_tbl_size;
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u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
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u32 val = 0;
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int ret;
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writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
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writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
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ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
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val, val & BIT(0), 200, 2000);
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if (ret)
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goto disable_power;
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writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
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ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
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val, val == 0, 200, 2000);
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if (ret)
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goto disable_power;
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writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
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core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
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writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
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writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
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writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
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reset_control_bulk_reset(clk_rst_tbl_size, core->resets);
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/* Disable MVP NoC clock */
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val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL);
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val |= NOC_HALT;
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writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL);
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/* enable MVP NoC reset */
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val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET);
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val |= SW_RESET;
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writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET);
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/* poll AON spare register bit0 to become zero with 50ms timeout */
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ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_SPARE,
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val, (val & BIT(0)) == 0, 1000, 50000);
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if (ret)
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goto disable_power;
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/* enable bit(1) to avoid cvp noc xo reset */
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val = readl(core->reg_base + AON_WRAPPER_SPARE);
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val |= BIT(1);
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writel(val, core->reg_base + AON_WRAPPER_SPARE);
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reset_control_bulk_assert(xo_rst_tbl_size, core->controller_resets);
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/* De-assert MVP NoC reset */
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val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET);
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val &= ~SW_RESET;
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writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET);
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usleep_range(80, 100);
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reset_control_bulk_deassert(xo_rst_tbl_size, core->controller_resets);
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/* reset AON spare register */
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writel(0, core->reg_base + AON_WRAPPER_SPARE);
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/* Enable MVP NoC clock */
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val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL);
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val &= ~NOC_HALT;
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writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL);
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iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
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disable_power:
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iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
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iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
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return 0;
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}
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static int iris_vpu35_power_on_hw(struct iris_core *core)
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{
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int ret;
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ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
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if (ret)
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return ret;
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ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
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if (ret)
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goto err_disable_power;
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ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);
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if (ret)
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goto err_disable_axi_clk;
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ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
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if (ret)
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goto err_disable_hw_free_clk;
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ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
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if (ret)
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goto err_disable_hw_clk;
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return 0;
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err_disable_hw_clk:
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iris_disable_unprepare_clock(core, IRIS_HW_CLK);
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err_disable_hw_free_clk:
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iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
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err_disable_axi_clk:
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iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
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err_disable_power:
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iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
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return ret;
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}
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static void iris_vpu35_power_off_hw(struct iris_core *core)
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{
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iris_vpu33_power_off_hardware(core);
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iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
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iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
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}
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const struct vpu_ops iris_vpu3_ops = {
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.power_off_hw = iris_vpu3_power_off_hardware,
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.power_on_hw = iris_vpu_power_on_hw,
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.power_off_controller = iris_vpu_power_off_controller,
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.power_on_controller = iris_vpu_power_on_controller,
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.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
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};
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const struct vpu_ops iris_vpu33_ops = {
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.power_off_hw = iris_vpu33_power_off_hardware,
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.power_on_hw = iris_vpu_power_on_hw,
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.power_off_controller = iris_vpu33_power_off_controller,
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.power_on_controller = iris_vpu_power_on_controller,
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.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
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};
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const struct vpu_ops iris_vpu35_ops = {
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.power_off_hw = iris_vpu35_power_off_hw,
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.power_on_hw = iris_vpu35_power_on_hw,
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.power_off_controller = iris_vpu35_vpu4x_power_off_controller,
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.power_on_controller = iris_vpu35_vpu4x_power_on_controller,
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.program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
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.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
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};
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