From cc303f75c562dc784ff7af0ec2b654787a5472fe Mon Sep 17 00:00:00 2001
From: Howon Lee <kck4156@kagamine-rin.com>
Date: Wed, 13 Nov 2024 02:45:16 +0900
Subject: [PATCH] Added support for Lunar Lake CPUs (#1520)

* Added support for Lunar Lake CPUs

* Fixed a typo
---
 .../Hardware/Cpu/IntelCpu.cs                  | 23 +++++++++++++------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
index f8766d8..c8f8daf 100644
--- a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
+++ b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
@@ -220,13 +220,18 @@ internal sealed class IntelCpu : GenericCpu
                         case 0xA7: // Intel Core i5, i6, i7 11xxx (14nm) (Rocket Lake)
                             _microArchitecture = MicroArchitecture.RocketLake;
                             tjMax = GetTjMaxFromMsr();
-                            break;
-
+                            break;
+
                         case 0xC6: // Intel Core Ultra 7 200 Series ArrowLake
                             _microArchitecture = MicroArchitecture.ArrowLake;
                             tjMax = GetTjMaxFromMsr();
-                            break;
-
+                            break;
+
+                        case 0xBD: // Intel Core Ultra 5/7 200 Series LunarLake
+                            _microArchitecture = MicroArchitecture.LunarLake;
+                            tjMax = GetTjMaxFromMsr();
+                            break;
+
                         default:
                             _microArchitecture = MicroArchitecture.Unknown;
                             tjMax = Floats(100);
@@ -272,7 +277,7 @@ internal sealed class IntelCpu : GenericCpu
 
                 break;
             case MicroArchitecture.Airmont:
-            case MicroArchitecture.AlderLake:
+            case MicroArchitecture.AlderLake:
             case MicroArchitecture.ArrowLake:
             case MicroArchitecture.Broadwell:
             case MicroArchitecture.CannonLake:
@@ -284,6 +289,7 @@ internal sealed class IntelCpu : GenericCpu
             case MicroArchitecture.IvyBridge:
             case MicroArchitecture.JasperLake:
             case MicroArchitecture.KabyLake:
+            case MicroArchitecture.LunarLake:
             case MicroArchitecture.Nehalem:
             case MicroArchitecture.MeteorLake:
             case MicroArchitecture.RaptorLake:
@@ -387,7 +393,7 @@ internal sealed class IntelCpu : GenericCpu
         }
 
         if (_microArchitecture is MicroArchitecture.Airmont or
-            MicroArchitecture.AlderLake or
+            MicroArchitecture.AlderLake or
             MicroArchitecture.ArrowLake or
             MicroArchitecture.Broadwell or
             MicroArchitecture.CannonLake or
@@ -399,6 +405,7 @@ internal sealed class IntelCpu : GenericCpu
             MicroArchitecture.IvyBridge or
             MicroArchitecture.JasperLake or
             MicroArchitecture.KabyLake or
+            MicroArchitecture.LunarLake or
             MicroArchitecture.MeteorLake or
             MicroArchitecture.RaptorLake or
             MicroArchitecture.RocketLake or
@@ -602,6 +609,7 @@ internal sealed class IntelCpu : GenericCpu
                         case MicroArchitecture.IvyBridge:
                         case MicroArchitecture.JasperLake:
                         case MicroArchitecture.KabyLake:
+                        case MicroArchitecture.LunarLake:
                         case MicroArchitecture.MeteorLake:
                         case MicroArchitecture.RaptorLake:
                         case MicroArchitecture.RocketLake:
@@ -609,7 +617,7 @@ internal sealed class IntelCpu : GenericCpu
                         case MicroArchitecture.Silvermont:
                         case MicroArchitecture.Skylake:
                         case MicroArchitecture.TigerLake:
-                        case MicroArchitecture.Tremont:
+                        case MicroArchitecture.Tremont:
                             _coreClocks[i].Value = (float)(((eax >> 8) & 0xff) * newBusClock);
                             break;
                         default:
@@ -690,6 +698,7 @@ internal sealed class IntelCpu : GenericCpu
         IvyBridge,
         JasperLake,
         KabyLake,
+        LunarLake,
         Nehalem,
         NetBurst,
         MeteorLake,