From a80b455eaa968a4caa6a20ca0af6a5ef321f443c Mon Sep 17 00:00:00 2001
From: Lucas Towers <luctowers@gmail.com>
Date: Sat, 14 Nov 2020 11:16:51 -0800
Subject: [PATCH] Add support for AMD Ryzen 5000 processors (#328)

* Add bare-minimum support for family 0x19

* Treat Zen 3 like Zen 2 in most-cases

* Remove mistakenly added whitespace
---
 LibreHardwareMonitorLib/Hardware/Cpu/Amd17Cpu.cs | 11 ++++++-----
 LibreHardwareMonitorLib/Hardware/Cpu/CpuGroup.cs |  1 +
 LibreHardwareMonitorLib/Hardware/Cpu/CpuId.cs    |  2 +-
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/LibreHardwareMonitorLib/Hardware/Cpu/Amd17Cpu.cs b/LibreHardwareMonitorLib/Hardware/Cpu/Amd17Cpu.cs
index 1dc253d..a80315d 100644
--- a/LibreHardwareMonitorLib/Hardware/Cpu/Amd17Cpu.cs
+++ b/LibreHardwareMonitorLib/Hardware/Cpu/Amd17Cpu.cs
@@ -164,7 +164,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
                     Ring0.WritePciConfig(0x00, FAMILY_17H_PCI_CONTROL_REGISTER, F17H_M01H_SVI + 0x8);
                     Ring0.ReadPciConfig(0x00, FAMILY_17H_PCI_CONTROL_REGISTER + 4, out smuSvi0Tfn);
 
-                    bool isZen2 = false;
+                    bool supportsPerCCDTemperatures = false;
 
                     // TODO: find a better way because these will probably keep changing in the future.
 
@@ -176,14 +176,15 @@ namespace LibreHardwareMonitor.Hardware.CPU
                         {
                             sviPlane0Offset = F17H_M01H_SVI + 0x14;
                             sviPlane1Offset = F17H_M01H_SVI + 0x10;
-                            isZen2 = true;
+                            supportsPerCCDTemperatures = true;
                             break;
                         }
                         case 0x71: // Zen 2.
+                        case 0x21: // Zen 3.
                         {
                             sviPlane0Offset = F17H_M01H_SVI + 0x10;
                             sviPlane1Offset = F17H_M01H_SVI + 0xC;
-                            isZen2 = true;
+                            supportsPerCCDTemperatures = true;
                             break;
                         }
                         default: // Zen and Zen+.
@@ -270,7 +271,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
                     }
 
                     // Tested only on R5 3600 & Threadripper 3960X.
-                    if (isZen2)
+                    if (supportsPerCCDTemperatures)
                     {
                         for (uint i = 0; i < _ccdTemperatures.Length; i++)
                         {
@@ -339,7 +340,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
                 }
 
                 // SoC (0x02), not every Zen cpu has this voltage.
-                if (cpu.Model == 0x71 || cpu.Model == 0x31 || (smuSvi0Tfn & 0x02) == 0)
+                if (cpu.Model == 0x21 || cpu.Model == 0x71 || cpu.Model == 0x31 || (smuSvi0Tfn & 0x02) == 0)
                 {
                     svi0PlaneXVddCor = (smuSvi0TelPlane1 >> 16) & 0xff;
                     vcc = 1.550 - vidStep * svi0PlaneXVddCor;
diff --git a/LibreHardwareMonitorLib/Hardware/Cpu/CpuGroup.cs b/LibreHardwareMonitorLib/Hardware/Cpu/CpuGroup.cs
index faa2e2a..90a4257 100644
--- a/LibreHardwareMonitorLib/Hardware/Cpu/CpuGroup.cs
+++ b/LibreHardwareMonitorLib/Hardware/Cpu/CpuGroup.cs
@@ -51,6 +51,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
                                 _hardware.Add(new Amd10Cpu(index, coreThreads, settings));
                                 break;
                             case 0x17:
+                            case 0x19:
                                 _hardware.Add(new Amd17Cpu(index, coreThreads, settings));
                                 break;
                             default:
diff --git a/LibreHardwareMonitorLib/Hardware/Cpu/CpuId.cs b/LibreHardwareMonitorLib/Hardware/Cpu/CpuId.cs
index dd6ce3e..e4b5d34 100644
--- a/LibreHardwareMonitorLib/Hardware/Cpu/CpuId.cs
+++ b/LibreHardwareMonitorLib/Hardware/Cpu/CpuId.cs
@@ -168,7 +168,7 @@ namespace LibreHardwareMonitor.Hardware.CPU
                     threadMaskWith = 0;
                     coreMaskWith = NextLog2(corePerPackage);
 
-                    if (Family == 0x17)
+                    if (Family == 0x17 || Family == 0x19)
                     {
                         // ApicIdCoreIdSize: APIC ID size.
                         // cores per DIE