From 8d612d20da14dc7144b14e65b431f8e2add1d5ad Mon Sep 17 00:00:00 2001
From: "Markus H." <57905025+MaHoBo@users.noreply.github.com>
Date: Tue, 4 Feb 2025 16:30:00 +0100
Subject: [PATCH] added support for Intel ElkhartLake (#1625)

* Intel Arrow Lake 200 added

* added SAPPHIRERAPIDS support

* changed naming from SAPPHIRERAPIDS to SapphireRapids

* added support for ElkhartLake
---
 .../Hardware/Cpu/IntelCpu.cs                  | 26 ++++++++++++-------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
index 0440e4a..289493a 100644
--- a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
+++ b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
@@ -230,10 +230,14 @@ internal sealed class IntelCpu : GenericCpu
                         case 0xBD: // Intel Core Ultra 5/7 200 Series LunarLake
                             _microArchitecture = MicroArchitecture.LunarLake;
                             tjMax = GetTjMaxFromMsr();
-                            break;
+                            break;
                         case 0x8F: // Intel Xeon W5-3435X // SapphireRapids 
                             _microArchitecture = MicroArchitecture.SapphireRapids;
                             tjMax = GetTjMaxFromMsr();
+                            break;
+                        case 0x96: // Intel Celeron ElkhartLake 
+                            _microArchitecture = MicroArchitecture.ElkhartLake;
+                            tjMax = GetTjMaxFromMsr();
                             break;
 
                         default:
@@ -301,8 +305,9 @@ internal sealed class IntelCpu : GenericCpu
             case MicroArchitecture.SandyBridge:
             case MicroArchitecture.Silvermont:
             case MicroArchitecture.Skylake:
-            case MicroArchitecture.TigerLake:
-            case MicroArchitecture.SapphireRapids:
+            case MicroArchitecture.TigerLake:
+            case MicroArchitecture.SapphireRapids:
+            case MicroArchitecture.ElkhartLake:
             case MicroArchitecture.Tremont:
                 if (Ring0.ReadMsr(MSR_PLATFORM_INFO, out eax, out uint _))
                     _timeStampCounterMultiplier = (eax >> 8) & 0xff;
@@ -418,8 +423,9 @@ internal sealed class IntelCpu : GenericCpu
             MicroArchitecture.SandyBridge or
             MicroArchitecture.Silvermont or
             MicroArchitecture.Skylake or
-            MicroArchitecture.TigerLake or
-            MicroArchitecture.SapphireRapids or
+            MicroArchitecture.TigerLake or
+            MicroArchitecture.SapphireRapids or
+            MicroArchitecture.ElkhartLake or
             MicroArchitecture.Tremont)
         {
             _powerSensors = new Sensor[_energyStatusMsrs.Length];
@@ -623,8 +629,9 @@ internal sealed class IntelCpu : GenericCpu
                         case MicroArchitecture.SandyBridge:
                         case MicroArchitecture.Silvermont:
                         case MicroArchitecture.Skylake:
-                        case MicroArchitecture.TigerLake:
-                        case MicroArchitecture.SapphireRapids:
+                        case MicroArchitecture.TigerLake:
+                        case MicroArchitecture.SapphireRapids:
+                        case MicroArchitecture.ElkhartLake:
                         case MicroArchitecture.Tremont:
                             _coreClocks[i].Value = (float)(((eax >> 8) & 0xff) * newBusClock);
                             break;
@@ -716,8 +723,9 @@ internal sealed class IntelCpu : GenericCpu
         Skylake,
         TigerLake,
         Tremont,
-        RaptorLake,
-        SapphireRapids,
+        RaptorLake,
+        SapphireRapids,
+        ElkhartLake,
         Unknown
     }