From 42e6a3eb1986792277af2e61feda0f512e65a3e2 Mon Sep 17 00:00:00 2001 From: Phyxion <7643972+Phyxion@users.noreply.github.com> Date: Mon, 2 Mar 2020 17:14:00 +0100 Subject: [PATCH] Add support for Intel Comet Lake Also add CORS header for https://github.com/openhardwaremonitor/openhardwaremonitor/issues/1234 --- LibreHardwareMonitor/Utilities/HttpServer.cs | 3 +- .../Hardware/Cpu/IntelCpu.cs | 101 ++++++++++-------- 2 files changed, 57 insertions(+), 47 deletions(-) diff --git a/LibreHardwareMonitor/Utilities/HttpServer.cs b/LibreHardwareMonitor/Utilities/HttpServer.cs index 21d5ccb..fe184ba 100644 --- a/LibreHardwareMonitor/Utilities/HttpServer.cs +++ b/LibreHardwareMonitor/Utilities/HttpServer.cs @@ -415,11 +415,12 @@ namespace LibreHardwareMonitor.Utilities #if DEBUG string responseContent = json.ToString(Newtonsoft.Json.Formatting.Indented); #else - var responseContent = json.ToString(Newtonsoft.Json.Formatting.None); + string responseContent = json.ToString(Newtonsoft.Json.Formatting.None); #endif byte[] buffer = Encoding.UTF8.GetBytes(responseContent); response.AddHeader("Cache-Control", "no-cache"); + response.AddHeader("Access-Control-Allow-Origin", "*"); response.ContentLength64 = buffer.Length; response.ContentType = "application/json"; diff --git a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs index cd25da3..d5cf6f1 100644 --- a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs +++ b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs @@ -170,6 +170,10 @@ namespace LibreHardwareMonitor.Hardware.CPU _microArchitecture = MicroArchitecture.IceLake; tjMax = GetTjMaxFromMsr(); break; + case 0xA6: // Intel Core i3, i5, i7 10xxxU (14nm) + _microArchitecture = MicroArchitecture.CometLake; + tjMax = GetTjMaxFromMsr(); + break; case 0x86: // Tremont (10nm) (Elkhart Lake, Skyhawk Lake) _microArchitecture = MicroArchitecture.Tremont; tjMax = GetTjMaxFromMsr(); @@ -214,29 +218,31 @@ namespace LibreHardwareMonitor.Hardware.CPU // set timeStampCounterMultiplier switch (_microArchitecture) { - case MicroArchitecture.NetBurst: case MicroArchitecture.Atom: case MicroArchitecture.Core: + case MicroArchitecture.NetBurst: { if (Ring0.ReadMsr(IA32_PERF_STATUS, out uint _, out uint edx)) { _timeStampCounterMultiplier = ((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1); } + + break; } - break; + case MicroArchitecture.Airmont: + case MicroArchitecture.Broadwell: + case MicroArchitecture.CannonLake: + case MicroArchitecture.CometLake: + case MicroArchitecture.Goldmont: + case MicroArchitecture.GoldmontPlus: + case MicroArchitecture.Haswell: + case MicroArchitecture.IceLake: + case MicroArchitecture.IvyBridge: + case MicroArchitecture.KabyLake: case MicroArchitecture.Nehalem: case MicroArchitecture.SandyBridge: - case MicroArchitecture.IvyBridge: - case MicroArchitecture.Haswell: - case MicroArchitecture.Broadwell: case MicroArchitecture.Silvermont: case MicroArchitecture.Skylake: - case MicroArchitecture.Airmont: - case MicroArchitecture.Goldmont: - case MicroArchitecture.KabyLake: - case MicroArchitecture.GoldmontPlus: - case MicroArchitecture.CannonLake: - case MicroArchitecture.IceLake: case MicroArchitecture.TigerLake: case MicroArchitecture.Tremont: { @@ -335,18 +341,19 @@ namespace LibreHardwareMonitor.Hardware.CPU ActivateSensor(_coreClocks[i]); } - if (_microArchitecture == MicroArchitecture.SandyBridge || - _microArchitecture == MicroArchitecture.IvyBridge || - _microArchitecture == MicroArchitecture.Haswell || + if (_microArchitecture == MicroArchitecture.Airmont || _microArchitecture == MicroArchitecture.Broadwell || - _microArchitecture == MicroArchitecture.Skylake || - _microArchitecture == MicroArchitecture.Silvermont || - _microArchitecture == MicroArchitecture.Airmont || - _microArchitecture == MicroArchitecture.Goldmont || - _microArchitecture == MicroArchitecture.KabyLake || - _microArchitecture == MicroArchitecture.GoldmontPlus || _microArchitecture == MicroArchitecture.CannonLake || + _microArchitecture == MicroArchitecture.CometLake || + _microArchitecture == MicroArchitecture.Goldmont || + _microArchitecture == MicroArchitecture.GoldmontPlus || + _microArchitecture == MicroArchitecture.Haswell || _microArchitecture == MicroArchitecture.IceLake || + _microArchitecture == MicroArchitecture.IvyBridge || + _microArchitecture == MicroArchitecture.KabyLake || + _microArchitecture == MicroArchitecture.SandyBridge || + _microArchitecture == MicroArchitecture.Silvermont || + _microArchitecture == MicroArchitecture.Skylake || _microArchitecture == MicroArchitecture.TigerLake || _microArchitecture == MicroArchitecture.Tremont) { @@ -495,7 +502,9 @@ namespace LibreHardwareMonitor.Hardware.CPU _packageTemperature.Value = tjMax - tSlope * deltaT; } else + { _packageTemperature.Value = null; + } } if (HasTimeStampCounter && _timeStampCounterMultiplier > 0) @@ -514,20 +523,20 @@ namespace LibreHardwareMonitor.Hardware.CPU uint multiplier = eax & 0xff; _coreClocks[i].Value = (float)(multiplier * newBusClock); break; - } - - case MicroArchitecture.SandyBridge: - case MicroArchitecture.IvyBridge: - case MicroArchitecture.Haswell: - case MicroArchitecture.Broadwell: - case MicroArchitecture.Silvermont: + } case MicroArchitecture.Airmont: - case MicroArchitecture.Skylake: - case MicroArchitecture.Goldmont: - case MicroArchitecture.KabyLake: - case MicroArchitecture.GoldmontPlus: + case MicroArchitecture.Broadwell: case MicroArchitecture.CannonLake: + case MicroArchitecture.CometLake: + case MicroArchitecture.Goldmont: + case MicroArchitecture.GoldmontPlus: + case MicroArchitecture.Haswell: case MicroArchitecture.IceLake: + case MicroArchitecture.IvyBridge: + case MicroArchitecture.KabyLake: + case MicroArchitecture.SandyBridge: + case MicroArchitecture.Silvermont: + case MicroArchitecture.Skylake: case MicroArchitecture.TigerLake: case MicroArchitecture.Tremont: { @@ -535,7 +544,6 @@ namespace LibreHardwareMonitor.Hardware.CPU _coreClocks[i].Value = (float)(multiplier * newBusClock); break; } - default: { double multiplier = ((eax >> 8) & 0x1f) + 0.5 * ((eax >> 14) & 1); @@ -586,25 +594,26 @@ namespace LibreHardwareMonitor.Hardware.CPU [SuppressMessage("ReSharper", "IdentifierTypo")] private enum MicroArchitecture { - Unknown, - NetBurst, - Core, - Atom, - Nehalem, - SandyBridge, - IvyBridge, - Haswell, - Broadwell, - Silvermont, - Skylake, Airmont, - KabyLake, + Atom, + Broadwell, + CannonLake, + CometLake, + Core, Goldmont, GoldmontPlus, - CannonLake, + Haswell, IceLake, + IvyBridge, + KabyLake, + Nehalem, + NetBurst, + SandyBridge, + Silvermont, + Skylake, TigerLake, - Tremont + Tremont, + Unknown } // ReSharper disable InconsistentNaming