From 08c1ee28059a66361e2da10dc1dfe74da46e7b20 Mon Sep 17 00:00:00 2001
From: "Markus H." <57905025+MaHoBo@users.noreply.github.com>
Date: Thu, 16 Jan 2025 15:10:53 +0100
Subject: [PATCH] SAPPHIRERAPIDS support added (#1555)

* Intel Arrow Lake 200 added

* added SAPPHIRERAPIDS support

* changed naming from SAPPHIRERAPIDS to SapphireRapids
---
 LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
index fb1a40a..0440e4a 100644
--- a/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
+++ b/LibreHardwareMonitorLib/Hardware/Cpu/IntelCpu.cs
@@ -230,6 +230,10 @@ internal sealed class IntelCpu : GenericCpu
                         case 0xBD: // Intel Core Ultra 5/7 200 Series LunarLake
                             _microArchitecture = MicroArchitecture.LunarLake;
                             tjMax = GetTjMaxFromMsr();
+                            break;
+                        case 0x8F: // Intel Xeon W5-3435X // SapphireRapids 
+                            _microArchitecture = MicroArchitecture.SapphireRapids;
+                            tjMax = GetTjMaxFromMsr();
                             break;
 
                         default:
@@ -297,7 +301,8 @@ internal sealed class IntelCpu : GenericCpu
             case MicroArchitecture.SandyBridge:
             case MicroArchitecture.Silvermont:
             case MicroArchitecture.Skylake:
-            case MicroArchitecture.TigerLake:
+            case MicroArchitecture.TigerLake:
+            case MicroArchitecture.SapphireRapids:
             case MicroArchitecture.Tremont:
                 if (Ring0.ReadMsr(MSR_PLATFORM_INFO, out eax, out uint _))
                     _timeStampCounterMultiplier = (eax >> 8) & 0xff;
@@ -413,7 +418,8 @@ internal sealed class IntelCpu : GenericCpu
             MicroArchitecture.SandyBridge or
             MicroArchitecture.Silvermont or
             MicroArchitecture.Skylake or
-            MicroArchitecture.TigerLake or
+            MicroArchitecture.TigerLake or
+            MicroArchitecture.SapphireRapids or
             MicroArchitecture.Tremont)
         {
             _powerSensors = new Sensor[_energyStatusMsrs.Length];
@@ -617,7 +623,8 @@ internal sealed class IntelCpu : GenericCpu
                         case MicroArchitecture.SandyBridge:
                         case MicroArchitecture.Silvermont:
                         case MicroArchitecture.Skylake:
-                        case MicroArchitecture.TigerLake:
+                        case MicroArchitecture.TigerLake:
+                        case MicroArchitecture.SapphireRapids:
                         case MicroArchitecture.Tremont:
                             _coreClocks[i].Value = (float)(((eax >> 8) & 0xff) * newBusClock);
                             break;
@@ -709,7 +716,8 @@ internal sealed class IntelCpu : GenericCpu
         Skylake,
         TigerLake,
         Tremont,
-        RaptorLake,
+        RaptorLake,
+        SapphireRapids,
         Unknown
     }